target/linux/brcm2708/patches-4.4/0523-drm-vc4-Add-support-for-double-clocked-modes.patch

   1 From 184580ac95b7fa05eaf5ee16393ddd6103493d0a Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Wed, 28 Sep 2016 19:01:48 -0700
   4 Subject: [PATCH] drm/vc4: Add support for double-clocked modes.
   5
   6 Now that we have infoframes to report the pixel repeat flag, we can
   7 start using it.  Fixes locking the 720x480i and 720x576i modes on my
   8 Dell 2408WFP.  Like the 1920x1080i case, they don't fit properly on
   9 the screen, though.
  10
  11 Signed-off-by: Eric Anholt <eric@anholt.net>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_crtc.c | 17 +++++++++++------
  14  drivers/gpu/drm/vc4/vc4_hdmi.c | 16 +++++++++++-----
  15  drivers/gpu/drm/vc4/vc4_regs.h |  2 ++
  16  3 files changed, 24 insertions(+), 11 deletions(-)
  17
  18 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  19 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  20 @@ -371,6 +371,7 @@ static void vc4_crtc_mode_set_nofb(struc
  21         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
  22                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
  23         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
  24 +       u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
  25         bool debug_dump_regs = false;
  26
  27         if (debug_dump_regs) {
  28 @@ -384,14 +385,17 @@ static void vc4_crtc_mode_set_nofb(struc
  29         CRTC_WRITE(PV_CONTROL, 0);
  30
  31         CRTC_WRITE(PV_HORZA,
  32 -                  VC4_SET_FIELD(mode->htotal - mode->hsync_end,
  33 +                  VC4_SET_FIELD((mode->htotal -
  34 +                                 mode->hsync_end) * pixel_rep,
  35                                  PV_HORZA_HBP) |
  36 -                  VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
  37 +                  VC4_SET_FIELD((mode->hsync_end -
  38 +                                 mode->hsync_start) * pixel_rep,
  39                                  PV_HORZA_HSYNC));
  40         CRTC_WRITE(PV_HORZB,
  41 -                  VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
  42 +                  VC4_SET_FIELD((mode->hsync_start -
  43 +                                 mode->hdisplay) * pixel_rep,
  44                                  PV_HORZB_HFP) |
  45 -                  VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
  46 +                  VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
  47
  48         CRTC_WRITE(PV_VERTA,
  49                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
  50 @@ -426,7 +430,7 @@ static void vc4_crtc_mode_set_nofb(struc
  51                            PV_VCONTROL_CONTINUOUS |
  52                            (is_dsi ? PV_VCONTROL_DSI : 0) |
  53                            PV_VCONTROL_INTERLACE |
  54 -                          VC4_SET_FIELD(mode->htotal / 2,
  55 +                          VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
  56                                          PV_VCONTROL_ODD_DELAY));
  57                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
  58         } else {
  59 @@ -435,12 +439,13 @@ static void vc4_crtc_mode_set_nofb(struc
  60                            (is_dsi ? PV_VCONTROL_DSI : 0));
  61         }
  62
  63 -       CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
  64 +       CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
  65
  66         CRTC_WRITE(PV_CONTROL,
  67                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
  68                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
  69                                  PV_CONTROL_FIFO_LEVEL) |
  70 +                  VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
  71                    PV_CONTROL_CLR_AT_START |
  72                    PV_CONTROL_TRIGGER_UNDERFLOW |
  73                    PV_CONTROL_WAIT_HSTART |
  74 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  75 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  76 @@ -411,6 +411,7 @@ static void vc4_hdmi_encoder_mode_set(st
  77         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
  78         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
  79         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
  80 +       u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
  81         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
  82                                    VC4_HDMI_VERTA_VSP) |
  83                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
  84 @@ -433,7 +434,8 @@ static void vc4_hdmi_encoder_mode_set(st
  85
  86         HD_WRITE(VC4_HD_VID_CTL, 0);
  87
  88 -       clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000);
  89 +       clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000 *
  90 +                    ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
  91
  92         HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
  93                    HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
  94 @@ -443,14 +445,18 @@ static void vc4_hdmi_encoder_mode_set(st
  95         HDMI_WRITE(VC4_HDMI_HORZA,
  96                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
  97                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
  98 -                  VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP));
  99 +                  VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 100 +                                VC4_HDMI_HORZA_HAP));
 101
 102         HDMI_WRITE(VC4_HDMI_HORZB,
 103 -                  VC4_SET_FIELD(mode->htotal - mode->hsync_end,
 104 +                  VC4_SET_FIELD((mode->htotal -
 105 +                                 mode->hsync_end) * pixel_rep,
 106                                  VC4_HDMI_HORZB_HBP) |
 107 -                  VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
 108 +                  VC4_SET_FIELD((mode->hsync_end -
 109 +                                 mode->hsync_start) * pixel_rep,
 110                                  VC4_HDMI_HORZB_HSP) |
 111 -                  VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
 112 +                  VC4_SET_FIELD((mode->hsync_start -
 113 +                                 mode->hdisplay) * pixel_rep,
 114                                  VC4_HDMI_HORZB_HFP));
 115
 116         HDMI_WRITE(VC4_HDMI_VERTA0, verta);
 117 --- a/drivers/gpu/drm/vc4/vc4_regs.h
 118 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
 119 @@ -175,6 +175,8 @@
 120  # define PV_CONTROL_CLR_AT_START               BIT(14)
 121  # define PV_CONTROL_TRIGGER_UNDERFLOW          BIT(13)
 122  # define PV_CONTROL_WAIT_HSTART                        BIT(12)
 123 +# define PV_CONTROL_PIXEL_REP_MASK             VC4_MASK(5, 4)
 124 +# define PV_CONTROL_PIXEL_REP_SHIFT            4
 125  # define PV_CONTROL_CLK_SELECT_DSI_VEC         0
 126  # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI    1
 127  # define PV_CONTROL_CLK_SELECT_MASK            VC4_MASK(3, 2)