target/linux/brcm2708/patches-4.4/0510-drm-vc4-Enable-limited-range-RGB-output-with-CEA-mod.patch

   1 From 330916bb64ca043ad03993aa4041edc99f68cf8f Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Thu, 15 Sep 2016 17:52:17 +0100
   4 Subject: [PATCH] drm/vc4: Enable limited range RGB output with CEA modes.
   5
   6 ---
   7  drivers/gpu/drm/vc4/vc4_hdmi.c | 28 ++++++++++++++++++++++++++--
   8  drivers/gpu/drm/vc4/vc4_regs.h |  9 ++++++++-
   9  2 files changed, 34 insertions(+), 3 deletions(-)
  10
  11 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  12 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  13 @@ -285,6 +285,7 @@ static void vc4_hdmi_encoder_mode_set(st
  14                                       struct drm_display_mode *unadjusted_mode,
  15                                       struct drm_display_mode *mode)
  16  {
  17 +       struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
  18         struct drm_device *dev = encoder->dev;
  19         struct vc4_dev *vc4 = to_vc4_dev(dev);
  20         bool debug_dump_regs = false;
  21 @@ -300,6 +301,7 @@ static void vc4_hdmi_encoder_mode_set(st
  22         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
  23                      VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
  24                                    VC4_HDMI_VERTB_VBP));
  25 +       u32 csc_ctl;
  26
  27         if (debug_dump_regs) {
  28                 DRM_INFO("HDMI regs before:\n");
  29 @@ -338,9 +340,31 @@ static void vc4_hdmi_encoder_mode_set(st
  30                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
  31                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
  32
  33 +       csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
  34 +                               VC4_HD_CSC_CTL_ORDER);
  35 +
  36 +       if (vc4_encoder->hdmi_monitor && drm_match_cea_mode(mode) != 0) {
  37 +               /* Enable limited range RGB output.  This matrix is:
  38 +                * [ 0      0      0.8594 16]
  39 +                * [ 0      0.8594 0      16]
  40 +                * [ 0.8594 0      0      16]
  41 +                * [ 0      0      0       1]
  42 +                */
  43 +               csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
  44 +               csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
  45 +               csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
  46 +                                        VC4_HD_CSC_CTL_MODE);
  47 +
  48 +               HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
  49 +               HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
  50 +               HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
  51 +               HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
  52 +               HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
  53 +               HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
  54 +       }
  55 +
  56         /* The RGB order applies even when CSC is disabled. */
  57 -       HD_WRITE(VC4_HD_CSC_CTL, VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
  58 -                                              VC4_HD_CSC_CTL_ORDER));
  59 +       HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
  60
  61         HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
  62
  63 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  64 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  65 @@ -530,10 +530,17 @@
  66  # define VC4_HD_CSC_CTL_MODE_SHIFT             2
  67  # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB   0
  68  # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB   1
  69 -# define VC4_HD_CSC_CTL_MODE_CUSTOM            2
  70 +# define VC4_HD_CSC_CTL_MODE_CUSTOM            3
  71  # define VC4_HD_CSC_CTL_RGB2YCC                        BIT(1)
  72  # define VC4_HD_CSC_CTL_ENABLE                 BIT(0)
  73
  74 +#define VC4_HD_CSC_12_11                       0x044
  75 +#define VC4_HD_CSC_14_13                       0x048
  76 +#define VC4_HD_CSC_22_21                       0x04c
  77 +#define VC4_HD_CSC_24_23                       0x050
  78 +#define VC4_HD_CSC_32_31                       0x054
  79 +#define VC4_HD_CSC_34_33                       0x058
  80 +
  81  #define VC4_HD_FRAME_COUNT                     0x068
  82
  83  /* HVS display list information. */