target/linux/brcm2708/patches-4.4/0477-drm-vc4-Move-validation-s-current-max-ip-into-the-va.patch

   1 From 71f1e833c8f76504921b3913d5a8da310318934f Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Sat, 2 Jul 2016 09:57:07 -0700
   4 Subject: [PATCH] drm/vc4: Move validation's current/max ip into the validation
   5  struct.
   6
   7 Reduces the argument count for some of the functions, and will be used
   8 more with the upcoming looping support.
   9
  10 Signed-off-by: Eric Anholt <eric@anholt.net>
  11 (cherry picked from commit d0566c2a2f2baacefe1eb75be8a001fdd6fe84a3)
  12 ---
  13  drivers/gpu/drm/vc4/vc4_validate_shaders.c | 54 +++++++++++++++++-------------
  14  1 file changed, 30 insertions(+), 24 deletions(-)
  15
  16 --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
  17 +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
  18 @@ -40,6 +40,14 @@
  19  #include "vc4_qpu_defines.h"
  20
  21  struct vc4_shader_validation_state {
  22 +       /* Current IP being validated. */
  23 +       uint32_t ip;
  24 +
  25 +       /* IP at the end of the BO, do not read shader[max_ip] */
  26 +       uint32_t max_ip;
  27 +
  28 +       uint64_t *shader;
  29 +
  30         struct vc4_texture_sample_info tmu_setup[2];
  31         int tmu_write_count[2];
  32
  33 @@ -129,11 +137,11 @@ record_texture_sample(struct vc4_validat
  34  }
  35
  36  static bool
  37 -check_tmu_write(uint64_t inst,
  38 -               struct vc4_validated_shader_info *validated_shader,
  39 +check_tmu_write(struct vc4_validated_shader_info *validated_shader,
  40                 struct vc4_shader_validation_state *validation_state,
  41                 bool is_mul)
  42  {
  43 +       uint64_t inst = validation_state->shader[validation_state->ip];
  44         uint32_t waddr = (is_mul ?
  45                           QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
  46                           QPU_GET_FIELD(inst, QPU_WADDR_ADD));
  47 @@ -228,11 +236,11 @@ check_tmu_write(uint64_t inst,
  48  }
  49
  50  static bool
  51 -check_reg_write(uint64_t inst,
  52 -               struct vc4_validated_shader_info *validated_shader,
  53 +check_reg_write(struct vc4_validated_shader_info *validated_shader,
  54                 struct vc4_shader_validation_state *validation_state,
  55                 bool is_mul)
  56  {
  57 +       uint64_t inst = validation_state->shader[validation_state->ip];
  58         uint32_t waddr = (is_mul ?
  59                           QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
  60                           QPU_GET_FIELD(inst, QPU_WADDR_ADD));
  61 @@ -261,7 +269,7 @@ check_reg_write(uint64_t inst,
  62         case QPU_W_TMU1_T:
  63         case QPU_W_TMU1_R:
  64         case QPU_W_TMU1_B:
  65 -               return check_tmu_write(inst, validated_shader, validation_state,
  66 +               return check_tmu_write(validated_shader, validation_state,
  67                                        is_mul);
  68
  69         case QPU_W_HOST_INT:
  70 @@ -294,10 +302,10 @@ check_reg_write(uint64_t inst,
  71  }
  72
  73  static void
  74 -track_live_clamps(uint64_t inst,
  75 -                 struct vc4_validated_shader_info *validated_shader,
  76 +track_live_clamps(struct vc4_validated_shader_info *validated_shader,
  77                   struct vc4_shader_validation_state *validation_state)
  78  {
  79 +       uint64_t inst = validation_state->shader[validation_state->ip];
  80         uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
  81         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
  82         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
  83 @@ -369,10 +377,10 @@ track_live_clamps(uint64_t inst,
  84  }
  85
  86  static bool
  87 -check_instruction_writes(uint64_t inst,
  88 -                        struct vc4_validated_shader_info *validated_shader,
  89 +check_instruction_writes(struct vc4_validated_shader_info *validated_shader,
  90                          struct vc4_shader_validation_state *validation_state)
  91  {
  92 +       uint64_t inst = validation_state->shader[validation_state->ip];
  93         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
  94         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
  95         bool ok;
  96 @@ -382,12 +390,10 @@ check_instruction_writes(uint64_t inst,
  97                 return false;
  98         }
  99
 100 -       ok = (check_reg_write(inst, validated_shader, validation_state,
 101 -                             false) &&
 102 -             check_reg_write(inst, validated_shader, validation_state,
 103 -                             true));
 104 +       ok = (check_reg_write(validated_shader, validation_state, false) &&
 105 +             check_reg_write(validated_shader, validation_state, true));
 106
 107 -       track_live_clamps(inst, validated_shader, validation_state);
 108 +       track_live_clamps(validated_shader, validation_state);
 109
 110         return ok;
 111  }
 112 @@ -417,30 +423,30 @@ vc4_validate_shader(struct drm_gem_cma_o
 113  {
 114         bool found_shader_end = false;
 115         int shader_end_ip = 0;
 116 -       uint32_t ip, max_ip;
 117 -       uint64_t *shader;
 118 +       uint32_t ip;
 119         struct vc4_validated_shader_info *validated_shader;
 120         struct vc4_shader_validation_state validation_state;
 121         int i;
 122
 123         memset(&validation_state, 0, sizeof(validation_state));
 124 +       validation_state.shader = shader_obj->vaddr;
 125 +       validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t);
 126
 127         for (i = 0; i < 8; i++)
 128                 validation_state.tmu_setup[i / 4].p_offset[i % 4] = ~0;
 129         for (i = 0; i < ARRAY_SIZE(validation_state.live_min_clamp_offsets); i++)
 130                 validation_state.live_min_clamp_offsets[i] = ~0;
 131
 132 -       shader = shader_obj->vaddr;
 133 -       max_ip = shader_obj->base.size / sizeof(uint64_t);
 134 -
 135         validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL);
 136         if (!validated_shader)
 137                 return NULL;
 138
 139 -       for (ip = 0; ip < max_ip; ip++) {
 140 -               uint64_t inst = shader[ip];
 141 +       for (ip = 0; ip < validation_state.max_ip; ip++) {
 142 +               uint64_t inst = validation_state.shader[ip];
 143                 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 144
 145 +               validation_state.ip = ip;
 146 +
 147                 switch (sig) {
 148                 case QPU_SIG_NONE:
 149                 case QPU_SIG_WAIT_FOR_SCOREBOARD:
 150 @@ -450,7 +456,7 @@ vc4_validate_shader(struct drm_gem_cma_o
 151                 case QPU_SIG_LOAD_TMU1:
 152                 case QPU_SIG_PROG_END:
 153                 case QPU_SIG_SMALL_IMM:
 154 -                       if (!check_instruction_writes(inst, validated_shader,
 155 +                       if (!check_instruction_writes(validated_shader,
 156                                                       &validation_state)) {
 157                                 DRM_ERROR("Bad write at ip %d\n", ip);
 158                                 goto fail;
 159 @@ -467,7 +473,7 @@ vc4_validate_shader(struct drm_gem_cma_o
 160                         break;
 161
 162                 case QPU_SIG_LOAD_IMM:
 163 -                       if (!check_instruction_writes(inst, validated_shader,
 164 +                       if (!check_instruction_writes(validated_shader,
 165                                                       &validation_state)) {
 166                                 DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
 167                                 goto fail;
 168 @@ -487,7 +493,7 @@ vc4_validate_shader(struct drm_gem_cma_o
 169                         break;
 170         }
 171
 172 -       if (ip == max_ip) {
 173 +       if (ip == validation_state.max_ip) {
 174                 DRM_ERROR("shader failed to terminate before "
 175                           "shader BO end at %zd\n",
 176                           shader_obj->base.size);