target/linux/brcm2708/patches-4.4/0441-drm-vc4-Add-support-for-feeding-DSI-encoders-from-th.patch

   1 From c50d2b2fc772468306a8b30159924f19edab4901 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Wed, 10 Feb 2016 16:17:29 -0800
   4 Subject: [PATCH] drm/vc4: Add support for feeding DSI encoders from the pixel
   5  valve.
   6
   7 Signed-off-by: Eric Anholt <eric@anholt.net>
   8 ---
   9  drivers/gpu/drm/vc4/vc4_crtc.c | 30 +++++++++++++++++-------------
  10  drivers/gpu/drm/vc4/vc4_regs.h |  2 ++
  11  2 files changed, 19 insertions(+), 13 deletions(-)
  12
  13 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  14 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  15 @@ -210,38 +210,40 @@ static u32 vc4_get_fifo_full_level(u32 f
  16  }
  17
  18  /*
  19 - * Returns the clock select bit for the connector attached to the
  20 - * CRTC.
  21 + * Returns the encoder attached to the CRTC.
  22 + *
  23 + * VC4 can only scan out to one encoder at a type, while the DRM core
  24 + * allows drivers to push pixels to more than one encoder from the
  25 + * same CRTC.
  26   */
  27 -static int vc4_get_clock_select(struct drm_crtc *crtc)
  28 +static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
  29  {
  30         struct drm_connector *connector;
  31
  32         drm_for_each_connector(connector, crtc->dev) {
  33                 if (connector->state->crtc == crtc) {
  34 -                       struct drm_encoder *encoder = connector->encoder;
  35 -                       struct vc4_encoder *vc4_encoder =
  36 -                               to_vc4_encoder(encoder);
  37 -
  38 -                       return vc4_encoder->clock_select;
  39 +                       return connector->encoder;
  40                 }
  41         }
  42
  43 -       return -1;
  44 +       return NULL;
  45  }
  46
  47  static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
  48  {
  49         struct drm_device *dev = crtc->dev;
  50         struct vc4_dev *vc4 = to_vc4_dev(dev);
  51 +       struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
  52 +       struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
  53         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  54         struct drm_crtc_state *state = crtc->state;
  55         struct drm_display_mode *mode = &state->adjusted_mode;
  56         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
  57         u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
  58 -       u32 format = PV_CONTROL_FORMAT_24;
  59 -       bool debug_dump_regs = false;
  60 -       int clock_select = vc4_get_clock_select(crtc);
  61 +       bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
  62 +                      vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
  63 +       u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
  64 +       bool debug_dump_regs = true;
  65
  66         if (debug_dump_regs) {
  67                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
  68 @@ -289,6 +291,7 @@ static void vc4_crtc_mode_set_nofb(struc
  69
  70         CRTC_WRITE(PV_V_CONTROL,
  71                    PV_VCONTROL_CONTINUOUS |
  72 +                  (is_dsi ? PV_VCONTROL_DSI : 0) |
  73                    (interlace ? PV_VCONTROL_INTERLACE : 0));
  74
  75         CRTC_WRITE(PV_CONTROL,
  76 @@ -298,7 +301,8 @@ static void vc4_crtc_mode_set_nofb(struc
  77                    PV_CONTROL_CLR_AT_START |
  78                    PV_CONTROL_TRIGGER_UNDERFLOW |
  79                    PV_CONTROL_WAIT_HSTART |
  80 -                  VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
  81 +                  VC4_SET_FIELD(vc4_encoder->clock_select,
  82 +                                PV_CONTROL_CLK_SELECT) |
  83                    PV_CONTROL_FIFO_CLR |
  84                    PV_CONTROL_EN);
  85
  86 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  87 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  88 @@ -184,6 +184,8 @@
  89
  90  #define PV_V_CONTROL                           0x04
  91  # define PV_VCONTROL_INTERLACE                 BIT(4)
  92 +# define PV_VCONTROL_DSI                       BIT(3)
  93 +# define PV_VCONTROL_COMMAND                   BIT(2)
  94  # define PV_VCONTROL_CONTINUOUS                        BIT(1)
  95  # define PV_VCONTROL_VIDEN                     BIT(0)
  96