686f5c6ac95c78dcf9dcb8d23ed637914557356a
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.4 / 0168-FIXUP-BCM270X_DT-Update-to-latest-Pi3-DTS.patch
1 From 52015bd5f0bb4d64ca51c5f8539cf2552dfb8a42 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.org>
3 Date: Thu, 21 Jan 2016 17:57:49 +0000
4 Subject: [PATCH 168/170] FIXUP: BCM270X_DT: Update to latest Pi3 DTS
5
6 ---
7 arch/arm/boot/dts/bcm2710-rpi-3-b.dts | 34 ++++++++++++++++++++++++++--------
8 1 file changed, 26 insertions(+), 8 deletions(-)
9
10 --- a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
11 +++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
12 @@ -45,16 +45,21 @@
13 };
14
15 bt_pins: bt_pins {
16 - brcm,pins = <28 29 30 31 14 15 43>;
17 - brcm,function = <6 6 6 6 2 2 4>;
18 - // alt2:PCM alt5:UART1 alt0:GPCLK2
19 - brcm,pull = <0 0 0 0 0 2 0>;
20 + brcm,pins = <28 29 30 31 43>;
21 + brcm,function = <6 6 6 6 4>; /* alt2:PCM alt0:GPCLK2 */
22 + brcm,pull = <0 0 0 0 0>;
23 };
24
25 - uart1_pins: uart1_pins {
26 + uart0_pins: uart0_pins {
27 brcm,pins = <32 33>;
28 brcm,function = <7>; /* alt3=UART0 */
29 - brcm,pull = <0>;
30 + brcm,pull = <0 0>;
31 + };
32 +
33 + uart1_pins: uart1_pins {
34 + brcm,pins = <14 15>;
35 + brcm,function = <2>; /* alt5=UART1 */
36 + brcm,pull = <0 0>;
37 };
38 };
39
40 @@ -71,6 +76,17 @@
41 non-removable;
42 bus-width = <4>;
43 status = "okay";
44 + brcm,overclock-50 = <0>;
45 +};
46 +
47 +&soc {
48 + virtgpio: virtgpio {
49 + compatible = "brcm,bcm2835-virtgpio";
50 + gpio-controller;
51 + #gpio-cells = <2>;
52 + firmware = <&firmware>;
53 + status = "okay";
54 + };
55 };
56
57 &fb {
58 @@ -78,12 +94,14 @@
59 };
60
61 &uart0 {
62 + pinctrl-names = "default";
63 + pinctrl-0 = <&uart0_pins &bt_pins>;
64 status = "okay";
65 };
66
67 &uart1 {
68 pinctrl-names = "default";
69 - pinctrl-0 = <&uart1_pins &bt_pins>;
70 + pinctrl-0 = <&uart1_pins>;
71 status = "okay";
72 };
73
74 @@ -139,7 +157,7 @@
75 act_led: act {
76 label = "led0";
77 linux,default-trigger = "mmc0";
78 - gpios = <&gpio 47 0>;
79 + gpios = <&virtgpio 0 0>;
80 };
81 };
82