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[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.19 / 950-0650-bcm2835-dma-Add-proper-40-bit-DMA-support.patch
1 From 511ed7aad02f375c8a5cc3c847e6b5fc4bf4a620 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.org>
3 Date: Thu, 4 Apr 2019 13:33:47 +0100
4 Subject: [PATCH 650/703] bcm2835-dma: Add proper 40-bit DMA support
5
6 The 40-bit additions are not fully tested, but it should be
7 capable of supporting both 40-bit memcpy on BCM2711 and regular
8 Lite channels on BCM2835.
9
10 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
11 ---
12 arch/arm/boot/dts/bcm2838.dtsi | 33 +-
13 drivers/dma/bcm2835-dma.c | 426 ++++++++++++++-----
14 drivers/pci/controller/pcie-brcmstb-bounce.c | 30 +-
15 drivers/pci/controller/pcie-brcmstb-bounce.h | 21 +-
16 drivers/pci/controller/pcie-brcmstb.c | 23 +-
17 5 files changed, 395 insertions(+), 138 deletions(-)
18
19 --- a/arch/arm/boot/dts/bcm2838.dtsi
20 +++ b/arch/arm/boot/dts/bcm2838.dtsi
21 @@ -372,6 +372,23 @@
22 };
23 };
24
25 + dma40: dma@7e007b00 {
26 + compatible = "brcm,bcm2838-dma";
27 + reg = <0x0 0x7e007b00 0x400>;
28 + interrupts =
29 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 11 */
30 + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 12 */
31 + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, /* dma4 13 */
32 + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; /* dma4 14 */
33 + interrupt-names = "dma11",
34 + "dma12",
35 + "dma13",
36 + "dma14";
37 + #dma-cells = <1>;
38 + brcm,dma-channel-mask = <0x7000>;
39 + };
40 + /* DMA4 - 40 bit DMA engines */
41 +
42 xhci: xhci@7e9c0000 {
43 compatible = "generic-xhci";
44 status = "disabled";
45 @@ -689,6 +706,7 @@
46 };
47
48 &dma {
49 + reg = <0x7e007000 0xb00>;
50 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
53 @@ -699,12 +717,7 @@
54 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 7 */
55 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 8 */
56 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 9 */
57 - <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 10 */
58 - /* DMA4 - 40 bit DMA engines */
59 - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 11 */
60 - <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 12 */
61 - <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, /* dma4 13 */
62 - <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; /* dma4 14 */
63 + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /* dmalite 10 */
64 interrupt-names = "dma0",
65 "dma1",
66 "dma2",
67 @@ -715,10 +728,6 @@
68 "dma7",
69 "dma8",
70 "dma9",
71 - "dma10",
72 - "dma11",
73 - "dma12",
74 - "dma13",
75 - "dma14";
76 - brcm,dma-channel-mask = <0x7ef5>;
77 + "dma10";
78 + brcm,dma-channel-mask = <0x01f5>;
79 };
80 --- a/drivers/dma/bcm2835-dma.c
81 +++ b/drivers/dma/bcm2835-dma.c
82 @@ -50,12 +50,18 @@
83 #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
84 #define BCM2835_DMA_CHAN_NAME_SIZE 8
85 #define BCM2835_DMA_BULK_MASK BIT(0)
86 +#define BCM2838_DMA_MEMCPY_CHAN 14
87 +
88 +struct bcm2835_dma_cfg_data {
89 + u32 chan_40bit_mask;
90 +};
91
92 struct bcm2835_dmadev {
93 struct dma_device ddev;
94 spinlock_t lock;
95 void __iomem *base;
96 struct device_dma_parameters dma_parms;
97 + const struct bcm2835_dma_cfg_data *cfg_data;
98 };
99
100 struct bcm2835_dma_cb {
101 @@ -100,6 +106,7 @@ struct bcm2835_chan {
102 unsigned int irq_flags;
103
104 bool is_lite_channel;
105 + bool is_40bit_channel;
106 };
107
108 struct bcm2835_desc {
109 @@ -189,7 +196,8 @@ struct bcm2835_desc {
110 #define BCM2835_DMA_DATA_TYPE_S128 16
111
112 /* Valid only for channels 0 - 14, 15 has its own base address */
113 -#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
114 +#define BCM2835_DMA_CHAN_SIZE 0x100
115 +#define BCM2835_DMA_CHAN(n) ((n) * BCM2835_DMA_CHAN_SIZE) /* Base address */
116 #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
117
118 /* the max dma length for different channels */
119 @@ -200,7 +208,7 @@ struct bcm2835_desc {
120 #define BCM2838_DMA40_CS 0x00
121 #define BCM2838_DMA40_CB 0x04
122 #define BCM2838_DMA40_DEBUG 0x0c
123 -#define BCM2858_DMA40_TI 0x10
124 +#define BCM2838_DMA40_TI 0x10
125 #define BCM2838_DMA40_SRC 0x14
126 #define BCM2838_DMA40_SRCI 0x18
127 #define BCM2838_DMA40_DEST 0x1c
128 @@ -209,32 +217,97 @@ struct bcm2835_desc {
129 #define BCM2838_DMA40_NEXT_CB 0x28
130 #define BCM2838_DMA40_DEBUG2 0x2c
131
132 -#define BCM2838_DMA40_CS_ACTIVE BIT(0)
133 -#define BCM2838_DMA40_CS_END BIT(1)
134 +#define BCM2838_DMA40_ACTIVE BIT(0)
135 +#define BCM2838_DMA40_END BIT(1)
136 +#define BCM2838_DMA40_INT BIT(2)
137 +#define BCM2838_DMA40_DREQ BIT(3) /* DREQ state */
138 +#define BCM2838_DMA40_RD_PAUSED BIT(4) /* Reading is paused */
139 +#define BCM2838_DMA40_WR_PAUSED BIT(5) /* Writing is paused */
140 +#define BCM2838_DMA40_DREQ_PAUSED BIT(6) /* Is paused by DREQ flow control */
141 +#define BCM2838_DMA40_WAITING_FOR_WRITES BIT(7) /* Waiting for last write */
142 +#define BCM2838_DMA40_ERR BIT(10)
143 +#define BCM2838_DMA40_QOS(x) (((x) & 0x1f) << 16)
144 +#define BCM2838_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20)
145 +#define BCM2838_DMA40_WAIT_FOR_WRITES BIT(28)
146 +#define BCM2838_DMA40_DISDEBUG BIT(29)
147 +#define BCM2838_DMA40_ABORT BIT(30)
148 +#define BCM2838_DMA40_HALT BIT(31)
149 +#define BCM2838_DMA40_CS_FLAGS(x) (x & (BCM2838_DMA40_QOS(15) | \
150 + BCM2838_DMA40_PANIC_QOS(15) | \
151 + BCM2838_DMA40_WAIT_FOR_WRITES | \
152 + BCM2838_DMA40_DISDEBUG))
153 +
154 +/* Transfer information bits */
155 +#define BCM2838_DMA40_INTEN BIT(0)
156 +#define BCM2838_DMA40_TDMODE BIT(1) /* 2D-Mode */
157 +#define BCM2838_DMA40_WAIT_RESP BIT(2) /* wait for AXI write to be acked */
158 +#define BCM2838_DMA40_WAIT_RD_RESP BIT(3) /* wait for AXI read to complete */
159 +#define BCM2838_DMA40_PER_MAP(x) ((x & 31) << 9) /* REQ source */
160 +#define BCM2838_DMA40_S_DREQ BIT(14) /* enable SREQ for source */
161 +#define BCM2838_DMA40_D_DREQ BIT(15) /* enable DREQ for destination */
162 +#define BCM2838_DMA40_S_WAIT(x) ((x & 0xff) << 16) /* add DMA read-wait cycles */
163 +#define BCM2838_DMA40_D_WAIT(x) ((x & 0xff) << 24) /* add DMA write-wait cycles */
164
165 -#define BCM2838_DMA40_CS_QOS(x) (((x) & 0x1f) << 16)
166 -#define BCM2838_DMA40_CS_PANIC_QOS(x) (((x) & 0x1f) << 20)
167 -#define BCM2838_DMA40_CS_WRITE_WAIT BIT(28)
168 +/* debug register bits */
169 +#define BCM2838_DMA40_DEBUG_WRITE_ERR BIT(0)
170 +#define BCM2838_DMA40_DEBUG_FIFO_ERR BIT(1)
171 +#define BCM2838_DMA40_DEBUG_READ_ERR BIT(2)
172 +#define BCM2838_DMA40_DEBUG_READ_CB_ERR BIT(3)
173 +#define BCM2838_DMA40_DEBUG_IN_ON_ERR BIT(8)
174 +#define BCM2838_DMA40_DEBUG_ABORT_ON_ERR BIT(9)
175 +#define BCM2838_DMA40_DEBUG_HALT_ON_ERR BIT(10)
176 +#define BCM2838_DMA40_DEBUG_DISABLE_CLK_GATE BIT(11)
177 +#define BCM2838_DMA40_DEBUG_RSTATE_SHIFT 14
178 +#define BCM2838_DMA40_DEBUG_RSTATE_BITS 4
179 +#define BCM2838_DMA40_DEBUG_WSTATE_SHIFT 18
180 +#define BCM2838_DMA40_DEBUG_WSTATE_BITS 4
181 +#define BCM2838_DMA40_DEBUG_RESET BIT(23)
182 +#define BCM2838_DMA40_DEBUG_ID_SHIFT 24
183 +#define BCM2838_DMA40_DEBUG_ID_BITS 4
184 +#define BCM2838_DMA40_DEBUG_VERSION_SHIFT 28
185 +#define BCM2838_DMA40_DEBUG_VERSION_BITS 4
186 +
187 +/* Valid only for channels 0 - 3 (11 - 14) */
188 +#define BCM2838_DMA40_CHAN(n) (((n) + 11) << 8) /* Base address */
189 +#define BCM2838_DMA40_CHANIO(base, n) ((base) + BCM2838_DMA_CHAN(n))
190
191 -#define BCM2838_DMA40_BURST_LEN(x) ((((x) - 1) & 0xf) << 8)
192 -#define BCM2838_DMA40_INC BIT(12)
193 -#define BCM2838_DMA40_SIZE_128 (2 << 13)
194 +/* the max dma length for different channels */
195 +#define MAX_DMA40_LEN SZ_1G
196
197 -#define BCM2838_DMA40_MEMCPY_QOS \
198 - (BCM2838_DMA40_CS_QOS(0x0) | \
199 - BCM2838_DMA40_CS_PANIC_QOS(0x0) | \
200 - BCM2838_DMA40_CS_WRITE_WAIT)
201 +#define BCM2838_DMA40_BURST_LEN(x) ((min(x,16) - 1) << 8)
202 +#define BCM2838_DMA40_INC BIT(12)
203 +#define BCM2838_DMA40_SIZE_32 (0 << 13)
204 +#define BCM2838_DMA40_SIZE_64 (1 << 13)
205 +#define BCM2838_DMA40_SIZE_128 (2 << 13)
206 +#define BCM2838_DMA40_SIZE_256 (3 << 13)
207 +#define BCM2838_DMA40_IGNORE BIT(15)
208 +#define BCM2838_DMA40_STRIDE(x) ((x) << 16) /* For 2D mode */
209 +
210 +#define BCM2838_DMA40_MEMCPY_FLAGS \
211 + (BCM2838_DMA40_QOS(0) | \
212 + BCM2838_DMA40_PANIC_QOS(0) | \
213 + BCM2838_DMA40_WAIT_FOR_WRITES | \
214 + BCM2838_DMA40_DISDEBUG)
215
216 #define BCM2838_DMA40_MEMCPY_XFER_INFO \
217 (BCM2838_DMA40_SIZE_128 | \
218 BCM2838_DMA40_INC | \
219 BCM2838_DMA40_BURST_LEN(16))
220
221 +struct bcm2835_dmadev *memcpy_parent;
222 static void __iomem *memcpy_chan;
223 static struct bcm2838_dma40_scb *memcpy_scb;
224 static dma_addr_t memcpy_scb_dma;
225 DEFINE_SPINLOCK(memcpy_lock);
226
227 +static const struct bcm2835_dma_cfg_data bcm2835_dma_cfg = {
228 + .chan_40bit_mask = 0,
229 +};
230 +
231 +static const struct bcm2835_dma_cfg_data bcm2838_dma_cfg = {
232 + .chan_40bit_mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
233 +};
234 +
235 static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)
236 {
237 /* lite and normal channels have different max frame length */
238 @@ -264,6 +337,32 @@ static inline struct bcm2835_desc *to_bc
239 return container_of(t, struct bcm2835_desc, vd.tx);
240 }
241
242 +static inline uint32_t to_bcm2838_ti(uint32_t info)
243 +{
244 + return ((info & BCM2835_DMA_INT_EN) ? BCM2838_DMA40_INTEN : 0) |
245 + ((info & BCM2835_DMA_WAIT_RESP) ? BCM2838_DMA40_WAIT_RESP : 0) |
246 + ((info & BCM2835_DMA_S_DREQ) ?
247 + (BCM2838_DMA40_S_DREQ | BCM2838_DMA40_WAIT_RD_RESP) : 0) |
248 + ((info & BCM2835_DMA_D_DREQ) ? BCM2838_DMA40_D_DREQ : 0) |
249 + BCM2838_DMA40_PER_MAP((info >> 16) & 0x1f);
250 +}
251 +
252 +static inline uint32_t to_bcm2838_srci(uint32_t info)
253 +{
254 + return ((info & BCM2835_DMA_S_INC) ? BCM2838_DMA40_INC : 0);
255 +}
256 +
257 +static inline uint32_t to_bcm2838_dsti(uint32_t info)
258 +{
259 + return ((info & BCM2835_DMA_D_INC) ? BCM2838_DMA40_INC : 0);
260 +}
261 +
262 +static inline uint32_t to_bcm2838_cbaddr(dma_addr_t addr)
263 +{
264 + BUG_ON(addr & 0x1f);
265 + return (addr >> 5);
266 +}
267 +
268 static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)
269 {
270 size_t i;
271 @@ -282,45 +381,53 @@ static void bcm2835_dma_desc_free(struct
272 }
273
274 static void bcm2835_dma_create_cb_set_length(
275 - struct bcm2835_chan *chan,
276 + struct bcm2835_chan *c,
277 struct bcm2835_dma_cb *control_block,
278 size_t len,
279 size_t period_len,
280 size_t *total_len,
281 u32 finalextrainfo)
282 {
283 - size_t max_len = bcm2835_dma_max_frame_length(chan);
284 + size_t max_len = bcm2835_dma_max_frame_length(c);
285 + uint32_t cb_len;
286
287 /* set the length taking lite-channel limitations into account */
288 - control_block->length = min_t(u32, len, max_len);
289 + cb_len = min_t(u32, len, max_len);
290
291 - /* finished if we have no period_length */
292 - if (!period_len)
293 - return;
294 + if (period_len) {
295 + /*
296 + * period_len means: that we need to generate
297 + * transfers that are terminating at every
298 + * multiple of period_len - this is typically
299 + * used to set the interrupt flag in info
300 + * which is required during cyclic transfers
301 + */
302
303 - /*
304 - * period_len means: that we need to generate
305 - * transfers that are terminating at every
306 - * multiple of period_len - this is typically
307 - * used to set the interrupt flag in info
308 - * which is required during cyclic transfers
309 - */
310 + /* have we filled in period_length yet? */
311 + if (*total_len + cb_len < period_len) {
312 + /* update number of bytes in this period so far */
313 + *total_len += cb_len;
314 + } else {
315 + /* calculate the length that remains to reach period_len */
316 + cb_len = period_len - *total_len;
317
318 - /* have we filled in period_length yet? */
319 - if (*total_len + control_block->length < period_len) {
320 - /* update number of bytes in this period so far */
321 - *total_len += control_block->length;
322 - return;
323 + /* reset total_length for next period */
324 + *total_len = 0;
325 + }
326 }
327
328 - /* calculate the length that remains to reach period_length */
329 - control_block->length = period_len - *total_len;
330 -
331 - /* reset total_length for next period */
332 - *total_len = 0;
333 -
334 - /* add extrainfo bits in info */
335 - control_block->info |= finalextrainfo;
336 + if (c->is_40bit_channel) {
337 + struct bcm2838_dma40_scb *scb =
338 + (struct bcm2838_dma40_scb *)control_block;
339 +
340 + scb->len = cb_len;
341 + /* add extrainfo bits to ti */
342 + scb->ti |= to_bcm2838_ti(finalextrainfo);
343 + } else {
344 + control_block->length = cb_len;
345 + /* add extrainfo bits to info */
346 + control_block->info |= finalextrainfo;
347 + }
348 }
349
350 static inline size_t bcm2835_dma_count_frames_for_sg(
351 @@ -343,7 +450,7 @@ static inline size_t bcm2835_dma_count_f
352 /**
353 * bcm2835_dma_create_cb_chain - create a control block and fills data in
354 *
355 - * @chan: the @dma_chan for which we run this
356 + * @c: the @bcm2835_chan for which we run this
357 * @direction: the direction in which we transfer
358 * @cyclic: it is a cyclic transfer
359 * @info: the default info bits to apply per controlblock
360 @@ -361,12 +468,11 @@ static inline size_t bcm2835_dma_count_f
361 * @gfp: the GFP flag to use for allocation
362 */
363 static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
364 - struct dma_chan *chan, enum dma_transfer_direction direction,
365 + struct bcm2835_chan *c, enum dma_transfer_direction direction,
366 bool cyclic, u32 info, u32 finalextrainfo, size_t frames,
367 dma_addr_t src, dma_addr_t dst, size_t buf_len,
368 size_t period_len, gfp_t gfp)
369 {
370 - struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
371 size_t len = buf_len, total_len;
372 size_t frame;
373 struct bcm2835_desc *d;
374 @@ -399,11 +505,23 @@ static struct bcm2835_desc *bcm2835_dma_
375
376 /* fill in the control block */
377 control_block = cb_entry->cb;
378 - control_block->info = info;
379 - control_block->src = src;
380 - control_block->dst = dst;
381 - control_block->stride = 0;
382 - control_block->next = 0;
383 + if (c->is_40bit_channel) {
384 + struct bcm2838_dma40_scb *scb =
385 + (struct bcm2838_dma40_scb *)control_block;
386 + scb->ti = to_bcm2838_ti(info);
387 + scb->src = lower_32_bits(src);
388 + scb->srci= upper_32_bits(src) | to_bcm2838_srci(info);
389 + scb->dst = lower_32_bits(dst);
390 + scb->dsti = upper_32_bits(dst) | to_bcm2838_dsti(info);
391 + scb->next_cb = 0;
392 + } else {
393 + control_block->info = info;
394 + control_block->src = src;
395 + control_block->dst = dst;
396 + control_block->stride = 0;
397 + control_block->next = 0;
398 + }
399 +
400 /* set up length in control_block if requested */
401 if (buf_len) {
402 /* calculate length honoring period_length */
403 @@ -417,7 +535,10 @@ static struct bcm2835_desc *bcm2835_dma_
404 }
405
406 /* link this the last controlblock */
407 - if (frame)
408 + if (frame && c->is_40bit_channel)
409 + d->cb_list[frame - 1].cb->next =
410 + to_bcm2838_cbaddr(cb_entry->paddr);
411 + if (frame && !c->is_40bit_channel)
412 d->cb_list[frame - 1].cb->next = cb_entry->paddr;
413
414 /* update src and dst and length */
415 @@ -431,7 +552,14 @@ static struct bcm2835_desc *bcm2835_dma_
416 }
417
418 /* the last frame requires extra flags */
419 - d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
420 + if (c->is_40bit_channel) {
421 + struct bcm2838_dma40_scb *scb =
422 + (struct bcm2838_dma40_scb *)d->cb_list[d->frames-1].cb;
423 +
424 + scb->ti |= to_bcm2838_ti(finalextrainfo);
425 + } else {
426 + d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
427 + }
428
429 /* detect a size missmatch */
430 if (buf_len && (d->size != buf_len))
431 @@ -445,28 +573,51 @@ error_cb:
432 }
433
434 static void bcm2835_dma_fill_cb_chain_with_sg(
435 - struct dma_chan *chan,
436 + struct bcm2835_chan *c,
437 enum dma_transfer_direction direction,
438 struct bcm2835_cb_entry *cb,
439 struct scatterlist *sgl,
440 unsigned int sg_len)
441 {
442 - struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
443 size_t len, max_len;
444 unsigned int i;
445 dma_addr_t addr;
446 struct scatterlist *sgent;
447
448 + pr_err("dma_fill_chain_with_sg(ch %d, dir %d):\n", c->ch, direction);
449 +
450 max_len = bcm2835_dma_max_frame_length(c);
451 for_each_sg(sgl, sgent, sg_len, i) {
452 - for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent);
453 - len > 0;
454 - addr += cb->cb->length, len -= cb->cb->length, cb++) {
455 - if (direction == DMA_DEV_TO_MEM)
456 - cb->cb->dst = addr;
457 - else
458 - cb->cb->src = addr;
459 - cb->cb->length = min(len, max_len);
460 + if (c->is_40bit_channel) {
461 + struct bcm2838_dma40_scb *scb =
462 + (struct bcm2838_dma40_scb *)cb->cb;
463 + for (addr = sg_dma_address(sgent),
464 + len = sg_dma_len(sgent);
465 + len > 0;
466 + addr += scb->len, len -= scb->len, scb++) {
467 + if (direction == DMA_DEV_TO_MEM) {
468 + scb->dst = lower_32_bits(addr);
469 + scb->dsti = upper_32_bits(addr) | BCM2838_DMA40_INC;
470 + } else {
471 + scb->src = lower_32_bits(addr);
472 + scb->srci = upper_32_bits(addr) | BCM2838_DMA40_INC;
473 + }
474 + scb->len = min(len, max_len);
475 + pr_err(" %llx, %x\n", (u64)addr, scb->len);
476 + }
477 + } else {
478 + for (addr = sg_dma_address(sgent),
479 + len = sg_dma_len(sgent);
480 + len > 0;
481 + addr += cb->cb->length, len -= cb->cb->length,
482 + cb++) {
483 + if (direction == DMA_DEV_TO_MEM)
484 + cb->cb->dst = addr;
485 + else
486 + cb->cb->src = addr;
487 + cb->cb->length = min(len, max_len);
488 + pr_err(" %llx, %x\n", (u64)addr, cb->cb->length);
489 + }
490 }
491 }
492 }
493 @@ -475,6 +626,10 @@ static int bcm2835_dma_abort(struct bcm2
494 {
495 void __iomem *chan_base = c->chan_base;
496 long int timeout = 10000;
497 + u32 wait_mask = BCM2835_DMA_WAITING_FOR_WRITES;
498 +
499 + if (c->is_40bit_channel)
500 + wait_mask = BCM2838_DMA40_WAITING_FOR_WRITES;
501
502 /*
503 * A zero control block address means the channel is idle.
504 @@ -487,8 +642,7 @@ static int bcm2835_dma_abort(struct bcm2
505 writel(0, chan_base + BCM2835_DMA_CS);
506
507 /* Wait for any current AXI transfer to complete */
508 - while ((readl(chan_base + BCM2835_DMA_CS) &
509 - BCM2835_DMA_WAITING_FOR_WRITES) && --timeout)
510 + while ((readl(chan_base + BCM2835_DMA_CS) & wait_mask) && --timeout)
511 cpu_relax();
512
513 /* Peripheral might be stuck and fail to signal AXI write responses */
514 @@ -505,6 +659,7 @@ static void bcm2835_dma_start_desc(struc
515 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
516 struct bcm2835_desc *d;
517
518 + pr_err("dma_start_desc(%px)\n", vd);
519 if (!vd) {
520 c->desc = NULL;
521 return;
522 @@ -514,9 +669,16 @@ static void bcm2835_dma_start_desc(struc
523
524 c->desc = d = to_bcm2835_dma_desc(&vd->tx);
525
526 - writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
527 - writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
528 - c->chan_base + BCM2835_DMA_CS);
529 + if (c->is_40bit_channel) {
530 + writel(to_bcm2838_cbaddr(d->cb_list[0].paddr),
531 + c->chan_base + BCM2838_DMA40_CB);
532 + writel(BCM2838_DMA40_ACTIVE | BCM2838_DMA40_CS_FLAGS(c->dreq),
533 + c->chan_base + BCM2838_DMA40_CS);
534 + } else {
535 + writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
536 + writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
537 + c->chan_base + BCM2835_DMA_CS);
538 + }
539 }
540
541 static irqreturn_t bcm2835_dma_callback(int irq, void *data)
542 @@ -544,7 +706,8 @@ static irqreturn_t bcm2835_dma_callback(
543 * will remain idle despite the ACTIVE flag being set.
544 */
545 writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE |
546 - BCM2835_DMA_CS_FLAGS(c->dreq),
547 + (c->is_40bit_channel ? BCM2838_DMA40_CS_FLAGS(c->dreq) :
548 + BCM2835_DMA_CS_FLAGS(c->dreq)),
549 c->chan_base + BCM2835_DMA_CS);
550
551 d = c->desc;
552 @@ -643,9 +806,17 @@ static enum dma_status bcm2835_dma_tx_st
553 struct bcm2835_desc *d = c->desc;
554 dma_addr_t pos;
555
556 - if (d->dir == DMA_MEM_TO_DEV)
557 + if (d->dir == DMA_MEM_TO_DEV && c->is_40bit_channel)
558 + pos = readl(c->chan_base + BCM2838_DMA40_SRC) +
559 + ((readl(c->chan_base + BCM2838_DMA40_SRCI) &
560 + 0xff) << 8);
561 + else if (d->dir == DMA_MEM_TO_DEV && !c->is_40bit_channel)
562 pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
563 - else if (d->dir == DMA_DEV_TO_MEM)
564 + else if (d->dir == DMA_DEV_TO_MEM && c->is_40bit_channel)
565 + pos = readl(c->chan_base + BCM2838_DMA40_DEST) +
566 + ((readl(c->chan_base + BCM2838_DMA40_DESTI) &
567 + 0xff) << 8);
568 + else if (d->dir == DMA_DEV_TO_MEM && !c->is_40bit_channel)
569 pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
570 else
571 pos = 0;
572 @@ -691,7 +862,7 @@ static struct dma_async_tx_descriptor *b
573 frames = bcm2835_dma_frames_for_length(len, max_len);
574
575 /* allocate the CB chain - this also fills in the pointers */
576 - d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false,
577 + d = bcm2835_dma_create_cb_chain(c, DMA_MEM_TO_MEM, false,
578 info, extra, frames,
579 src, dst, len, 0, GFP_KERNEL);
580 if (!d)
581 @@ -726,11 +897,21 @@ static struct dma_async_tx_descriptor *b
582 if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
583 return NULL;
584 src = c->cfg.src_addr;
585 + /*
586 + * One would think it ought to be possible to get the physical
587 + * to dma address mapping information from the dma-ranges DT
588 + * property, but I've not found a way yet that doesn't involve
589 + * open-coding the whole thing.
590 + */
591 + if (c->is_40bit_channel)
592 + src |= 0x400000000ull;
593 info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
594 } else {
595 if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
596 return NULL;
597 dst = c->cfg.dst_addr;
598 + if (c->is_40bit_channel)
599 + dst |= 0x400000000ull;
600 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
601 }
602
603 @@ -738,7 +919,7 @@ static struct dma_async_tx_descriptor *b
604 frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len);
605
606 /* allocate the CB chain */
607 - d = bcm2835_dma_create_cb_chain(chan, direction, false,
608 + d = bcm2835_dma_create_cb_chain(c, direction, false,
609 info, extra,
610 frames, src, dst, 0, 0,
611 GFP_KERNEL);
612 @@ -746,7 +927,7 @@ static struct dma_async_tx_descriptor *b
613 return NULL;
614
615 /* fill in frames with scatterlist pointers */
616 - bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list,
617 + bcm2835_dma_fill_cb_chain_with_sg(c, direction, d->cb_list,
618 sgl, sg_len);
619
620 return vchan_tx_prep(&c->vc, &d->vd, flags);
621 @@ -815,7 +996,7 @@ static struct dma_async_tx_descriptor *b
622 * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine
623 * implementation calls prep_dma_cyclic with interrupts disabled.
624 */
625 - d = bcm2835_dma_create_cb_chain(chan, direction, true,
626 + d = bcm2835_dma_create_cb_chain(c, direction, true,
627 info, extra,
628 frames, src, dst, buf_len,
629 period_len, GFP_NOWAIT);
630 @@ -823,7 +1004,8 @@ static struct dma_async_tx_descriptor *b
631 return NULL;
632
633 /* wrap around into a loop */
634 - d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
635 + d->cb_list[d->frames - 1].cb->next = c->is_40bit_channel ?
636 + to_bcm2838_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr;
637
638 return vchan_tx_prep(&c->vc, &d->vd, flags);
639 }
640 @@ -899,9 +1081,11 @@ static int bcm2835_dma_chan_init(struct
641 c->irq_number = irq;
642 c->irq_flags = irq_flags;
643
644 - /* check in DEBUG register if this is a LITE channel */
645 - if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
646 - BCM2835_DMA_DEBUG_LITE)
647 + /* check for 40bit and lite channels */
648 + if (d->cfg_data->chan_40bit_mask & BIT(chan_id))
649 + c->is_40bit_channel = true;
650 + else if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
651 + BCM2835_DMA_DEBUG_LITE)
652 c->is_lite_channel = true;
653
654 return 0;
655 @@ -918,18 +1102,16 @@ static void bcm2835_dma_free(struct bcm2
656 }
657 }
658
659 -int bcm2838_dma40_memcpy_init(struct device *dev)
660 +int bcm2838_dma40_memcpy_init(void)
661 {
662 - if (memcpy_scb)
663 - return 0;
664 + if (!memcpy_parent)
665 + return -EPROBE_DEFER;
666
667 - memcpy_scb = dma_alloc_coherent(dev, sizeof(*memcpy_scb),
668 - &memcpy_scb_dma, GFP_KERNEL);
669 + if (!memcpy_chan)
670 + return -EINVAL;
671
672 - if (!memcpy_scb) {
673 - pr_err("bcm2838_dma40_memcpy_init failed!\n");
674 + if (!memcpy_scb)
675 return -ENOMEM;
676 - }
677
678 return 0;
679 }
680 @@ -956,20 +1138,22 @@ void bcm2838_dma40_memcpy(dma_addr_t dst
681 scb->next_cb = 0;
682
683 writel((u32)(memcpy_scb_dma >> 5), memcpy_chan + BCM2838_DMA40_CB);
684 - writel(BCM2838_DMA40_MEMCPY_QOS + BCM2838_DMA40_CS_ACTIVE,
685 + writel(BCM2838_DMA40_MEMCPY_FLAGS + BCM2838_DMA40_ACTIVE,
686 memcpy_chan + BCM2838_DMA40_CS);
687 +
688 /* Poll for completion */
689 - while (!(readl(memcpy_chan + BCM2838_DMA40_CS) & BCM2838_DMA40_CS_END))
690 + while (!(readl(memcpy_chan + BCM2838_DMA40_CS) & BCM2838_DMA40_END))
691 cpu_relax();
692
693 - writel(BCM2838_DMA40_CS_END, memcpy_chan + BCM2838_DMA40_CS);
694 + writel(BCM2838_DMA40_END, memcpy_chan + BCM2838_DMA40_CS);
695
696 spin_unlock_irqrestore(&memcpy_lock, flags);
697 }
698 EXPORT_SYMBOL(bcm2838_dma40_memcpy);
699
700 static const struct of_device_id bcm2835_dma_of_match[] = {
701 - { .compatible = "brcm,bcm2835-dma", },
702 + { .compatible = "brcm,bcm2835-dma", .data = &bcm2835_dma_cfg },
703 + { .compatible = "brcm,bcm2838-dma", .data = &bcm2838_dma_cfg },
704 {},
705 };
706 MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
707 @@ -1001,6 +1185,8 @@ static int bcm2835_dma_probe(struct plat
708 int irq_flags;
709 uint32_t chans_available;
710 char chan_name[BCM2835_DMA_CHAN_NAME_SIZE];
711 + const struct of_device_id *of_id;
712 + int chan_count, chan_start, chan_end;
713
714 if (!pdev->dev.dma_mask)
715 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
716 @@ -1020,9 +1206,13 @@ static int bcm2835_dma_probe(struct plat
717 base = devm_ioremap_resource(&pdev->dev, res);
718 if (IS_ERR(base))
719 return PTR_ERR(base);
720 - rc = bcm_dmaman_probe(pdev, base, BCM2835_DMA_BULK_MASK);
721 - if (rc)
722 - dev_err(&pdev->dev, "Failed to initialize the legacy API\n");
723 +
724 + /* The set of channels can be split across multiple instances. */
725 + chan_start = ((u32)base / BCM2835_DMA_CHAN_SIZE) & 0xf;
726 + base -= BCM2835_DMA_CHAN(chan_start);
727 + chan_count = resource_size(res) / BCM2835_DMA_CHAN_SIZE;
728 + chan_end = min(chan_start + chan_count,
729 + BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1);
730
731 od->base = base;
732
733 @@ -1052,6 +1242,14 @@ static int bcm2835_dma_probe(struct plat
734
735 platform_set_drvdata(pdev, od);
736
737 + of_id = of_match_node(bcm2835_dma_of_match, pdev->dev.of_node);
738 + if (!of_id) {
739 + dev_err(&pdev->dev, "Failed to match compatible string\n");
740 + return -EINVAL;
741 + }
742 +
743 + od->cfg_data = of_id->data;
744 +
745 /* Request DMA channel mask from device tree */
746 if (of_property_read_u32(pdev->dev.of_node,
747 "brcm,dma-channel-mask",
748 @@ -1061,18 +1259,34 @@ static int bcm2835_dma_probe(struct plat
749 goto err_no_dma;
750 }
751
752 - /* Channel 0 is used by the legacy API */
753 - chans_available &= ~BCM2835_DMA_BULK_MASK;
754 + /* One channel is reserved for the legacy API */
755 + if (chans_available & BCM2835_DMA_BULK_MASK) {
756 + rc = bcm_dmaman_probe(pdev, base,
757 + chans_available & BCM2835_DMA_BULK_MASK);
758 + if (rc)
759 + dev_err(&pdev->dev,
760 + "Failed to initialize the legacy API\n");
761 +
762 + chans_available &= ~BCM2835_DMA_BULK_MASK;
763 + }
764
765 - /* We can't use channels 11-13 yet */
766 - chans_available &= ~(BIT(11) | BIT(12) | BIT(13));
767 + /* And possibly one for the 40-bit DMA memcpy API */
768 + if (chans_available & od->cfg_data->chan_40bit_mask &
769 + BIT(BCM2838_DMA_MEMCPY_CHAN)) {
770 + memcpy_parent = od;
771 + memcpy_chan = BCM2835_DMA_CHANIO(base, BCM2838_DMA_MEMCPY_CHAN);
772 + memcpy_scb = dma_alloc_coherent(memcpy_parent->ddev.dev,
773 + sizeof(*memcpy_scb),
774 + &memcpy_scb_dma, GFP_KERNEL);
775 + if (!memcpy_scb)
776 + dev_warn(&pdev->dev,
777 + "Failed to allocated memcpy scb\n");
778
779 - /* Grab channel 14 for the 40-bit DMA memcpy */
780 - chans_available &= ~BIT(14);
781 - memcpy_chan = BCM2835_DMA_CHANIO(base, 14);
782 + chans_available &= ~BIT(BCM2838_DMA_MEMCPY_CHAN);
783 + }
784
785 /* get irqs for each channel that we support */
786 - for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
787 + for (i = chan_start; i < chan_end; i++) {
788 /* skip masked out channels */
789 if (!(chans_available & (1 << i))) {
790 irq[i] = -1;
791 @@ -1095,13 +1309,17 @@ static int bcm2835_dma_probe(struct plat
792 irq[i] = platform_get_irq(pdev, i < 11 ? i : 11);
793 }
794
795 + chan_count = 0;
796 +
797 /* get irqs for each channel */
798 - for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
799 + for (i = chan_start; i < chan_end; i++) {
800 /* skip channels without irq */
801 if (irq[i] < 0)
802 continue;
803
804 /* check if there are other channels that also use this irq */
805 + /* FIXME: This will fail if interrupts are shared across
806 + instances */
807 irq_flags = 0;
808 for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++)
809 if ((i != j) && (irq[j] == irq[i])) {
810 @@ -1113,9 +1331,10 @@ static int bcm2835_dma_probe(struct plat
811 rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags);
812 if (rc)
813 goto err_no_dma;
814 + chan_count++;
815 }
816
817 - dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
818 + dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", chan_count);
819
820 /* Device-tree DMA controller registration */
821 rc = of_dma_controller_register(pdev->dev.of_node,
822 @@ -1147,6 +1366,13 @@ static int bcm2835_dma_remove(struct pla
823
824 bcm_dmaman_remove(pdev);
825 dma_async_device_unregister(&od->ddev);
826 + if (memcpy_parent == od) {
827 + dma_free_coherent(&pdev->dev, sizeof(*memcpy_scb), memcpy_scb,
828 + memcpy_scb_dma);
829 + memcpy_parent = NULL;
830 + memcpy_scb = NULL;
831 + memcpy_chan = NULL;
832 + }
833 bcm2835_dma_free(od);
834
835 return 0;
836 --- a/drivers/pci/controller/pcie-brcmstb-bounce.c
837 +++ b/drivers/pci/controller/pcie-brcmstb-bounce.c
838 @@ -91,7 +91,7 @@ struct dmabounce_device_info {
839
840 static struct dmabounce_device_info *g_dmabounce_device_info;
841
842 -extern int bcm2838_dma40_memcpy_init(struct device *dev);
843 +extern int bcm2838_dma40_memcpy_init(void);
844 extern void bcm2838_dma40_memcpy(dma_addr_t dst, dma_addr_t src, size_t size);
845
846 #ifdef STATS
847 @@ -471,9 +471,9 @@ static const struct dma_map_ops dmabounc
848 .mapping_error = dmabounce_mapping_error,
849 };
850
851 -int brcm_pcie_bounce_register_dev(struct device *dev,
852 - unsigned long buffer_size,
853 - dma_addr_t threshold)
854 +int brcm_pcie_bounce_init(struct device *dev,
855 + unsigned long buffer_size,
856 + dma_addr_t threshold)
857 {
858 struct dmabounce_device_info *device_info;
859 int ret;
860 @@ -482,9 +482,9 @@ int brcm_pcie_bounce_register_dev(struct
861 if (g_dmabounce_device_info)
862 return -EBUSY;
863
864 - ret = bcm2838_dma40_memcpy_init(dev);
865 + ret = bcm2838_dma40_memcpy_init();
866 if (ret)
867 - return ret;
868 + return ret;
869
870 device_info = kmalloc(sizeof(struct dmabounce_device_info), GFP_ATOMIC);
871 if (!device_info) {
872 @@ -515,9 +515,8 @@ int brcm_pcie_bounce_register_dev(struct
873 device_create_file(dev, &dev_attr_dmabounce_stats));
874
875 g_dmabounce_device_info = device_info;
876 - set_dma_ops(dev, &dmabounce_ops);
877
878 - dev_info(dev, "dmabounce: registered device - %ld kB, threshold %pad\n",
879 + dev_info(dev, "dmabounce: initialised - %ld kB, threshold %pad\n",
880 buffer_size / 1024, &threshold);
881
882 return 0;
883 @@ -526,14 +525,13 @@ int brcm_pcie_bounce_register_dev(struct
884 kfree(device_info);
885 return ret;
886 }
887 -EXPORT_SYMBOL(brcm_pcie_bounce_register_dev);
888 +EXPORT_SYMBOL(brcm_pcie_bounce_init);
889
890 -void brcm_pcie_bounce_unregister_dev(struct device *dev)
891 +void brcm_pcie_bounce_uninit(struct device *dev)
892 {
893 struct dmabounce_device_info *device_info = g_dmabounce_device_info;
894
895 g_dmabounce_device_info = NULL;
896 - set_dma_ops(dev, NULL);
897
898 if (!device_info) {
899 dev_warn(dev,
900 @@ -554,10 +552,16 @@ void brcm_pcie_bounce_unregister_dev(str
901 device_remove_file(dev, &dev_attr_dmabounce_stats));
902
903 kfree(device_info);
904 +}
905 +EXPORT_SYMBOL(brcm_pcie_bounce_uninit);
906 +
907 +int brcm_pcie_bounce_register_dev(struct device *dev)
908 +{
909 + set_dma_ops(dev, &dmabounce_ops);
910
911 - dev_info(dev, "dmabounce: device unregistered\n");
912 + return 0;
913 }
914 -EXPORT_SYMBOL(brcm_pcie_bounce_unregister_dev);
915 +EXPORT_SYMBOL(brcm_pcie_bounce_register_dev);
916
917 MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.org>");
918 MODULE_DESCRIPTION("Dedicate DMA bounce support for pcie-brcmstb");
919 --- a/drivers/pci/controller/pcie-brcmstb-bounce.h
920 +++ b/drivers/pci/controller/pcie-brcmstb-bounce.h
921 @@ -8,21 +8,26 @@
922
923 #ifdef CONFIG_ARM
924
925 -int brcm_pcie_bounce_register_dev(struct device *dev, unsigned long buffer_size,
926 - dma_addr_t threshold);
927 -
928 -int brcm_pcie_bounce_unregister_dev(struct device *dev);
929 +int brcm_pcie_bounce_init(struct device *dev, unsigned long buffer_size,
930 + dma_addr_t threshold);
931 +int brcm_pcie_bounce_uninit(struct device *dev);
932 +int brcm_pcie_bounce_register_dev(struct device *dev);
933
934 #else
935
936 -static inline int brcm_pcie_bounce_register_dev(struct device *dev,
937 - unsigned long buffer_size,
938 - dma_addr_t threshold)
939 +static inline int brcm_pcie_bounce_init(struct device *dev,
940 + unsigned long buffer_size,
941 + dma_addr_t threshold)
942 +{
943 + return 0;
944 +}
945 +
946 +static inline int brcm_pcie_bounce_uninit(struct device *dev)
947 {
948 return 0;
949 }
950
951 -static inline int brcm_pcie_bounce_unregister_dev(struct device *dev)
952 +static inline int brcm_pcie_bounce_register_dev(struct device *dev)
953 {
954 return 0;
955 }
956 --- a/drivers/pci/controller/pcie-brcmstb.c
957 +++ b/drivers/pci/controller/pcie-brcmstb.c
958 @@ -650,6 +650,7 @@ static void brcm_set_dma_ops(struct devi
959
960 static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
961 unsigned int val);
962 +
963 static int brcmstb_platform_notifier(struct notifier_block *nb,
964 unsigned long event, void *__dev)
965 {
966 @@ -663,12 +664,11 @@ static int brcmstb_platform_notifier(str
967 strcmp(dev->kobj.name, rc_name)) {
968 int ret;
969
970 - ret = brcm_pcie_bounce_register_dev(dev, bounce_buffer,
971 - (dma_addr_t)bounce_threshold);
972 + ret = brcm_pcie_bounce_register_dev(dev);
973 if (ret) {
974 dev_err(dev,
975 "brcm_pcie_bounce_register_dev() failed: %d\n",
976 - ret);
977 + ret);
978 return ret;
979 }
980 }
981 @@ -681,8 +681,6 @@ static int brcmstb_platform_notifier(str
982 brcm_pcie_perst_set(g_pcie, 1);
983 msleep(100);
984 brcm_pcie_perst_set(g_pcie, 0);
985 - } else if (max_pfn > (bounce_threshold/PAGE_SIZE)) {
986 - brcm_pcie_bounce_unregister_dev(dev);
987 }
988 return NOTIFY_OK;
989
990 @@ -1718,6 +1716,7 @@ static int brcm_pcie_probe(struct platfo
991 void __iomem *base;
992 struct pci_host_bridge *bridge;
993 struct pci_bus *child;
994 + extern unsigned long max_pfn;
995
996 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
997 if (!bridge)
998 @@ -1753,6 +1752,20 @@ static int brcm_pcie_probe(struct platfo
999 if (IS_ERR(base))
1000 return PTR_ERR(base);
1001
1002 + /* To Do: Add hardware check if this ever gets fixed */
1003 + if (max_pfn > (bounce_threshold/PAGE_SIZE)) {
1004 + int ret;
1005 + ret = brcm_pcie_bounce_init(&pdev->dev, bounce_buffer,
1006 + (dma_addr_t)bounce_threshold);
1007 + if (ret) {
1008 + if (ret != -EPROBE_DEFER)
1009 + dev_err(&pdev->dev,
1010 + "could not init bounce buffers: %d\n",
1011 + ret);
1012 + return ret;
1013 + }
1014 + }
1015 +
1016 pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
1017 if (IS_ERR(pcie->clk)) {
1018 dev_warn(&pdev->dev, "could not get clock\n");
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