0ac1269166bda08b285c9a6415588bb6861b2dc2
[openwrt/openwrt.git] / target / linux / bmips / dts / bcm6368.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /dts-v1/;
4
5 #include <dt-bindings/clock/bcm6368-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/bcm6368-reset.h>
11
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "brcm,bcm6368";
16
17 aliases {
18 nflash = &nflash;
19 pflash = &pflash;
20 pinctrl = &pinctrl;
21 serial0 = &uart0;
22 serial1 = &uart1;
23 spi0 = &lsspi;
24 };
25
26 chosen {
27 bootargs = "earlycon";
28 stdout-path = "serial0:115200n8";
29 };
30
31 clocks {
32 periph_osc: periph-osc {
33 compatible = "fixed-clock";
34
35 #clock-cells = <0>;
36
37 clock-frequency = <50000000>;
38 clock-output-names = "periph";
39 };
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45 mips-hpt-frequency = <200000000>;
46
47 cpu@0 {
48 compatible = "brcm,bmips4350", "mips,mips4Kc";
49 device_type = "cpu";
50 reg = <0>;
51 };
52
53 cpu@1 {
54 compatible = "brcm,bmips4350", "mips,mips4Kc";
55 device_type = "cpu";
56 reg = <1>;
57 };
58 };
59
60 cpu_intc: interrupt-controller {
61 #address-cells = <0>;
62 compatible = "mti,cpu-interrupt-controller";
63
64 interrupt-controller;
65 #interrupt-cells = <1>;
66 };
67
68 memory@0 {
69 device_type = "memory";
70 reg = <0 0>;
71 };
72
73 ubus {
74 #address-cells = <1>;
75 #size-cells = <1>;
76
77 compatible = "simple-bus";
78 ranges;
79
80 periph_clk: clock-controller@10000004 {
81 compatible = "brcm,bcm6368-clocks";
82 reg = <0x10000004 0x4>;
83 #clock-cells = <1>;
84 };
85
86 pll_cntl: syscon@10000008 {
87 compatible = "syscon", "simple-mfd";
88 reg = <0x10000008 0x4>;
89 native-endian;
90
91 syscon-reboot {
92 compatible = "syscon-reboot";
93 offset = <0x0>;
94 mask = <0x1>;
95 };
96 };
97
98 periph_rst: reset-controller@10000010 {
99 compatible = "brcm,bcm6345-reset";
100 reg = <0x10000010 0x4>;
101 #reset-cells = <1>;
102 };
103
104 ext_intc0: interrupt-controller@10000018 {
105 #address-cells = <1>;
106 compatible = "brcm,bcm6345-ext-intc";
107 reg = <0x10000018 0x4>;
108
109 interrupt-controller;
110 #interrupt-cells = <2>;
111
112 interrupt-parent = <&periph_intc>;
113 interrupts = <BCM6368_IRQ_EXT0>,
114 <BCM6368_IRQ_EXT1>,
115 <BCM6368_IRQ_EXT2>,
116 <BCM6368_IRQ_EXT3>;
117 };
118
119 ext_intc1: interrupt-controller@1000001c {
120 #address-cells = <1>;
121 compatible = "brcm,bcm6345-ext-intc";
122 reg = <0x1000001c 0x4>;
123
124 interrupt-controller;
125 #interrupt-cells = <2>;
126
127 interrupt-parent = <&periph_intc>;
128 interrupts = <BCM6368_IRQ_EXT4>,
129 <BCM6368_IRQ_EXT5>;
130 };
131
132 periph_intc: interrupt-controller@10000020 {
133 #address-cells = <1>;
134 compatible = "brcm,bcm6345-l1-intc";
135 reg = <0x10000020 0x10>,
136 <0x10000030 0x10>;
137
138 interrupt-controller;
139 #interrupt-cells = <1>;
140
141 interrupt-parent = <&cpu_intc>;
142 interrupts = <2>, <3>;
143 };
144
145 wdt: watchdog@1000005c {
146 compatible = "brcm,bcm7038-wdt";
147 reg = <0x1000005c 0xc>;
148
149 clocks = <&periph_osc>;
150
151 timeout-sec = <30>;
152 };
153
154 gpio_cntl: syscon@10000080 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 compatible = "brcm,bcm6368-gpio-sysctl",
158 "syscon", "simple-mfd";
159 reg = <0x10000080 0x80>;
160 ranges = <0 0x10000080 0x80>;
161 native-endian;
162
163 gpio: gpio@0 {
164 compatible = "brcm,bcm6368-gpio";
165 reg-names = "dirout", "dat";
166 reg = <0x0 0x8>, <0x8 0x8>;
167
168 gpio-controller;
169 gpio-ranges = <&pinctrl 0 0 38>;
170 #gpio-cells = <2>;
171 };
172
173 pinctrl: pinctrl@18 {
174 compatible = "brcm,bcm6368-pinctrl";
175 reg = <0x18 0x4>, <0x38 0x4>;
176
177 pinctrl_analog_afe_0: analog_afe_0-pins {
178 function = "analog_afe_0";
179 pins = "gpio0";
180 };
181
182 pinctrl_analog_afe_1: analog_afe_1-pins {
183 function = "analog_afe_1";
184 pins = "gpio1";
185 };
186
187 pinctrl_sys_irq: sys_irq-pins {
188 function = "sys_irq";
189 pins = "gpio2";
190 };
191
192 pinctrl_serial_led: serial_led-pins {
193 pinctrl_serial_led_data: serial_led_data-pins {
194 function = "serial_led_data";
195 pins = "gpio3";
196 };
197
198 pinctrl_serial_led_clk: serial_led_clk-pins {
199 function = "serial_led_clk";
200 pins = "gpio4";
201 };
202 };
203
204 pinctrl_inet_led: inet_led-pins {
205 function = "inet_led";
206 pins = "gpio5";
207 };
208
209 pinctrl_ephy0_led: ephy0_led-pins {
210 function = "ephy0_led";
211 pins = "gpio6";
212 };
213
214 pinctrl_ephy1_led: ephy1_led-pins {
215 function = "ephy1_led";
216 pins = "gpio7";
217 };
218
219 pinctrl_ephy2_led: ephy2_led-pins {
220 function = "ephy2_led";
221 pins = "gpio8";
222 };
223
224 pinctrl_ephy3_led: ephy3_led-pins {
225 function = "ephy3_led";
226 pins = "gpio9";
227 };
228
229 pinctrl_robosw_led_data: robosw_led_data-pins {
230 function = "robosw_led_data";
231 pins = "gpio10";
232 };
233
234 pinctrl_robosw_led_clk: robosw_led_clk-pins {
235 function = "robosw_led_clk";
236 pins = "gpio11";
237 };
238
239 pinctrl_robosw_led0: robosw_led0-pins {
240 function = "robosw_led0";
241 pins = "gpio12";
242 };
243
244 pinctrl_robosw_led1: robosw_led1-pins {
245 function = "robosw_led1";
246 pins = "gpio13";
247 };
248
249 pinctrl_usb_device_led: usb_device_led-pins {
250 function = "usb_device_led";
251 pins = "gpio14";
252 };
253
254 pinctrl_pci: pci-pins {
255 pinctrl_pci_req1: pci_req1-pins {
256 function = "pci_req1";
257 pins = "gpio16";
258 };
259
260 pinctrl_pci_gnt1: pci_gnt1-pins {
261 function = "pci_gnt1";
262 pins = "gpio17";
263 };
264
265 pinctrl_pci_intb: pci_intb-pins {
266 function = "pci_intb";
267 pins = "gpio18";
268 };
269
270 pinctrl_pci_req0: pci_req0-pins {
271 function = "pci_req0";
272 pins = "gpio19";
273 };
274
275 pinctrl_pci_gnt0: pci_gnt0-pins {
276 function = "pci_gnt0";
277 pins = "gpio20";
278 };
279 };
280
281 pinctrl_pcmcia: pcmcia-pins {
282 pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
283 function = "pcmcia_cd1";
284 pins = "gpio22";
285 };
286
287 pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
288 function = "pcmcia_cd2";
289 pins = "gpio23";
290 };
291
292 pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
293 function = "pcmcia_vs1";
294 pins = "gpio24";
295 };
296
297 pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
298 function = "pcmcia_vs2";
299 pins = "gpio25";
300 };
301 };
302
303 pinctrl_ebi_cs2: ebi_cs2-pins {
304 function = "ebi_cs2";
305 pins = "gpio26";
306 };
307
308 pinctrl_ebi_cs3: ebi_cs3-pins {
309 function = "ebi_cs3";
310 pins = "gpio27";
311 };
312
313 pinctrl_spi_cs2: spi_cs2-pins {
314 function = "spi_cs2";
315 pins = "gpio28";
316 };
317
318 pinctrl_spi_cs3: spi_cs3-pins {
319 function = "spi_cs3";
320 pins = "gpio29";
321 };
322
323 pinctrl_spi_cs4: spi_cs4-pins {
324 function = "spi_cs4";
325 pins = "gpio30";
326 };
327
328 pinctrl_spi_cs5: spi_cs5-pins {
329 function = "spi_cs5";
330 pins = "gpio31";
331 };
332
333 pinctrl_uart1: uart1-pins {
334 function = "uart1";
335 group = "uart1_grp";
336 };
337 };
338 };
339
340 leds: led-controller@100000d0 {
341 #address-cells = <1>;
342 #size-cells = <0>;
343 compatible = "brcm,bcm6358-leds";
344 reg = <0x100000d0 0x8>;
345
346 status = "disabled";
347 };
348
349 uart0: serial@10000100 {
350 compatible = "brcm,bcm6345-uart";
351 reg = <0x10000100 0x18>;
352
353 interrupt-parent = <&periph_intc>;
354 interrupts = <BCM6368_IRQ_UART0>;
355
356 clocks = <&periph_osc>;
357 clock-names = "periph";
358
359 status = "disabled";
360 };
361
362 uart1: serial@10000120 {
363 compatible = "brcm,bcm6345-uart";
364 reg = <0x10000120 0x18>;
365
366 interrupt-parent = <&periph_intc>;
367 interrupts = <BCM6368_IRQ_UART1>;
368
369 clocks = <&periph_osc>;
370 clock-names = "periph";
371
372 status = "disabled";
373 };
374
375 nflash: nand@10000200 {
376 #address-cells = <1>;
377 #size-cells = <0>;
378 compatible = "brcm,nand-bcm6368",
379 "brcm,brcmnand-v2.1",
380 "brcm,brcmnand";
381 reg = <0x10000200 0x180>,
382 <0x10000600 0x200>,
383 <0x10000070 0x10>;
384 reg-names = "nand",
385 "nand-cache",
386 "nand-int-base";
387
388 interrupt-parent = <&periph_intc>;
389 interrupts = <BCM6368_IRQ_NAND>;
390
391 clocks = <&periph_clk BCM6368_CLK_NAND>;
392 clock-names = "nand";
393
394 status = "disabled";
395 };
396
397 lsspi: spi@10000800 {
398 #address-cells = <1>;
399 #size-cells = <0>;
400 compatible = "brcm,bcm6358-spi";
401 reg = <0x10000800 0x70c>;
402
403 interrupt-parent = <&periph_intc>;
404 interrupts = <BCM6368_IRQ_SPI>;
405
406 clocks = <&periph_clk BCM6368_CLK_SPI>;
407 clock-names = "spi";
408
409 resets = <&periph_rst BCM6368_RST_SPI>;
410
411 status = "disabled";
412 };
413
414 pci: pci@10001000 {
415 compatible = "brcm,bcm6348-pci";
416 reg = <0x10001000 0x200>;
417 #address-cells = <3>;
418 #size-cells = <2>;
419
420 device_type = "pci";
421 bus-range = <0x00 0x01>;
422 ranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>,
423 <0x1000000 0 0x08000000 0x08000000 0 0x0010000>;
424 linux,pci-probe-only = <1>;
425
426 interrupt-parent = <&periph_intc>;
427 interrupts = <BCM6368_IRQ_MPI>;
428
429 resets = <&periph_rst BCM6368_RST_MPI>;
430 reset-names = "pci";
431
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_pci>;
434
435 brcm,remap;
436
437 status = "disabled";
438 };
439
440 ehci: usb@10001500 {
441 compatible = "brcm,bcm6368-ehci", "generic-ehci";
442 reg = <0x10001500 0x100>;
443 big-endian;
444 spurious-oc;
445
446 interrupt-parent = <&periph_intc>;
447 interrupts = <BCM6368_IRQ_EHCI>;
448
449 phys = <&usbh 0>;
450 phy-names = "usb";
451
452 status = "disabled";
453 };
454
455 ohci: usb@10001600 {
456 compatible = "brcm,bcm6368-ohci", "generic-ohci";
457 reg = <0x10001600 0x100>;
458 big-endian;
459 no-big-frame-no;
460
461 interrupt-parent = <&periph_intc>;
462 interrupts = <BCM6368_IRQ_OHCI>;
463
464 phys = <&usbh 0>;
465 phy-names = "usb";
466
467 status = "disabled";
468 };
469
470 usbh: usb-phy@10001700 {
471 compatible = "brcm,bcm6368-usbh-phy";
472 reg = <0x10001700 0x38>;
473
474 #phy-cells = <1>;
475
476 clocks = <&periph_clk BCM6368_CLK_USBH>;
477 clock-names = "usbh";
478
479 resets = <&periph_rst BCM6368_RST_USBH>;
480
481 status = "disabled";
482 };
483
484 random: rng@10004180 {
485 compatible = "brcm,bcm6368-rng";
486 reg = <0x10004180 0x14>;
487
488 clocks = <&periph_clk BCM6368_CLK_IPSEC>;
489 clock-names = "ipsec";
490
491 resets = <&periph_rst BCM6368_RST_IPSEC>;
492 };
493
494 ethernet: ethernet@10006800 {
495 compatible = "brcm,bcm6368-enetsw";
496 reg = <0x10006800 0x80>,
497 <0x10006a00 0x80>,
498 <0x10006c00 0x80>;
499 reg-names = "dma",
500 "dma-channels",
501 "dma-sram";
502
503 interrupt-parent = <&periph_intc>;
504 interrupts = <BCM6368_IRQ_ENETSW_RX_DMA0>,
505 <BCM6368_IRQ_ENETSW_TX_DMA0>;
506 interrupt-names = "rx",
507 "tx";
508
509 clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,
510 <&periph_clk BCM6368_CLK_SWPKT_SAR>,
511 <&periph_clk BCM6368_CLK_ROBOSW>;
512
513 resets = <&periph_rst BCM6368_RST_SWITCH>,
514 <&periph_rst BCM6368_RST_EPHY>;
515
516 dma-rx = <0>;
517 dma-tx = <1>;
518
519 status = "disabled";
520 };
521
522 switch0: switch@10f00000 {
523 #address-cells = <1>;
524 #size-cells = <0>;
525 compatible = "brcm,bcm6368-switch";
526 reg = <0x10f00000 0x8000>;
527 big-endian;
528
529 ports {
530 #address-cells = <1>;
531 #size-cells = <0>;
532
533 port@8 {
534 reg = <8>;
535
536 phy-mode = "internal";
537 ethernet = <&ethernet>;
538
539 fixed-link {
540 speed = <1000>;
541 full-duplex;
542 };
543 };
544 };
545 };
546
547 mdio: mdio@10f000b0 {
548 #address-cells = <1>;
549 #size-cells = <0>;
550 compatible = "brcm,bcm6368-mdio-mux";
551 reg = <0x10f000b0 0x8>;
552
553 mdio_int: mdio@0 {
554 #address-cells = <1>;
555 #size-cells = <0>;
556 reg = <0>;
557
558 phy1: ethernet-phy@1 {
559 compatible = "ethernet-phy-ieee802.3-c22";
560 reg = <1>;
561 };
562
563 phy2: ethernet-phy@2 {
564 compatible = "ethernet-phy-ieee802.3-c22";
565 reg = <2>;
566 };
567
568 phy3: ethernet-phy@3 {
569 compatible = "ethernet-phy-ieee802.3-c22";
570 reg = <3>;
571 };
572
573 phy4: ethernet-phy@4 {
574 compatible = "ethernet-phy-ieee802.3-c22";
575 reg = <4>;
576 };
577 };
578
579 mdio_ext: mdio@1 {
580 #address-cells = <1>;
581 #size-cells = <0>;
582 reg = <1>;
583 };
584 };
585 };
586
587 pflash: nor@18000000 {
588 #address-cells = <1>;
589 #size-cells = <1>;
590 compatible = "cfi-flash";
591 reg = <0x18000000 0x2000000>;
592 bank-width = <2>;
593
594 status = "disabled";
595 };
596 };