target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch

   1 From 7c70cb333deb6e2f88da9c94ddd6b3b00c97b93a Mon Sep 17 00:00:00 2001
   2 From: Jon Mason <jonmason@broadcom.com>
   3 Date: Thu, 15 Oct 2015 15:48:26 -0400
   4 Subject: [PATCH 45/50] clk: iproc: Add PWRCTRL support
   5
   6 Some iProc SoC clocks use a different way to control clock power, via
   7 the PWRDWN bit in the PLL control register.  Since the PLL control
   8 register is used to access the PWRDWN bit, there is no need for the
   9 pwr_base when this is being used.  A new flag, IPROC_CLK_EMBED_PWRCTRL,
  10 has been added to identify this usage.  We can use the AON interface to
  11 write the values to enable/disable PWRDOWN.
  12
  13 Signed-off-by: Jon Mason <jonmason@broadcom.com>
  14 ---
  15  drivers/clk/bcm/clk-iproc-pll.c | 55 ++++++++++++++++++++++++++++-------------
  16  drivers/clk/bcm/clk-iproc.h     |  6 +++++
  17  2 files changed, 44 insertions(+), 17 deletions(-)
  18
  19 --- a/drivers/clk/bcm/clk-iproc-pll.c
  20 +++ b/drivers/clk/bcm/clk-iproc-pll.c
  21 @@ -148,14 +148,25 @@ static void __pll_disable(struct iproc_p
  22                 writel(val, pll->asiu_base + ctrl->asiu.offset);
  23         }
  24
  25 -       /* latch input value so core power can be shut down */
  26 -       val = readl(pll->pwr_base + ctrl->aon.offset);
  27 -       val |= (1 << ctrl->aon.iso_shift);
  28 -       writel(val, pll->pwr_base + ctrl->aon.offset);
  29 -
  30 -       /* power down the core */
  31 -       val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
  32 -       writel(val, pll->pwr_base + ctrl->aon.offset);
  33 +       if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
  34 +               val = readl(pll->pll_base + ctrl->aon.offset);
  35 +               val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
  36 +               writel(val, pll->pll_base + ctrl->aon.offset);
  37 +
  38 +               if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
  39 +                       readl(pll->pll_base + ctrl->aon.offset);
  40 +       }
  41 +
  42 +       if (pll->pwr_base) {
  43 +               /* latch input value so core power can be shut down */
  44 +               val = readl(pll->pwr_base + ctrl->aon.offset);
  45 +               val |= (1 << ctrl->aon.iso_shift);
  46 +               writel(val, pll->pwr_base + ctrl->aon.offset);
  47 +
  48 +               /* power down the core */
  49 +               val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
  50 +               writel(val, pll->pwr_base + ctrl->aon.offset);
  51 +       }
  52  }
  53
  54  static int __pll_enable(struct iproc_pll *pll)
  55 @@ -163,11 +174,22 @@ static int __pll_enable(struct iproc_pll
  56         const struct iproc_pll_ctrl *ctrl = pll->ctrl;
  57         u32 val;
  58
  59 -       /* power up the PLL and make sure it's not latched */
  60 -       val = readl(pll->pwr_base + ctrl->aon.offset);
  61 -       val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
  62 -       val &= ~(1 << ctrl->aon.iso_shift);
  63 -       writel(val, pll->pwr_base + ctrl->aon.offset);
  64 +       if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) {
  65 +               val = readl(pll->pll_base + ctrl->aon.offset);
  66 +               val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
  67 +               writel(val, pll->pll_base + ctrl->aon.offset);
  68 +
  69 +               if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
  70 +                       readl(pll->pll_base + ctrl->aon.offset);
  71 +       }
  72 +
  73 +       if (pll->pwr_base) {
  74 +               /* power up the PLL and make sure it's not latched */
  75 +               val = readl(pll->pwr_base + ctrl->aon.offset);
  76 +               val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
  77 +               val &= ~(1 << ctrl->aon.iso_shift);
  78 +               writel(val, pll->pwr_base + ctrl->aon.offset);
  79 +       }
  80
  81         /* certain PLLs also need to be ungated from the ASIU top level */
  82         if (ctrl->flags & IPROC_CLK_PLL_ASIU) {
  83 @@ -607,9 +629,8 @@ void __init iproc_pll_clk_setup(struct d
  84         if (WARN_ON(!pll->pll_base))
  85                 goto err_pll_iomap;
  86
  87 +       /* Some SoCs do not require the pwr_base, thus failing is not fatal */
  88         pll->pwr_base = of_iomap(node, 1);
  89 -       if (WARN_ON(!pll->pwr_base))
  90 -               goto err_pwr_iomap;
  91
  92         /* some PLLs require gating control at the top ASIU level */
  93         if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) {
  94 @@ -692,9 +713,9 @@ err_pll_register:
  95                 iounmap(pll->asiu_base);
  96
  97  err_asiu_iomap:
  98 -       iounmap(pll->pwr_base);
  99 +       if (pll->pwr_base)
 100 +               iounmap(pll->pwr_base);
 101
 102 -err_pwr_iomap:
 103         iounmap(pll->pll_base);
 104
 105  err_pll_iomap:
 106 --- a/drivers/clk/bcm/clk-iproc.h
 107 +++ b/drivers/clk/bcm/clk-iproc.h
 108 @@ -49,6 +49,12 @@
 109  #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
 110
 111  /*
 112 + * Some PLLs use a different way to control clock power, via the PWRDWN bit in
 113 + * the PLL control register
 114 + */
 115 +#define IPROC_CLK_EMBED_PWRCTRL BIT(5)
 116 +
 117 +/*
 118   * Parameters for VCO frequency configuration
 119   *
 120   * VCO frequency =