target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch

   1 From b5116083e227fa478e20d5ed945430088aa1a00b Mon Sep 17 00:00:00 2001
   2 From: Jon Mason <jonmason@broadcom.com>
   3 Date: Thu, 15 Oct 2015 15:48:25 -0400
   4 Subject: [PATCH 44/50] clk: cygnus: Convert all macros to all caps
   5
   6 The macros that are being used to initialize the values of the clk
   7 structures should be all caps.  Find and replace all of them with their
   8 relevant counterparts.
   9
  10 Signed-off-by: Jon Mason <jonmason@broadcom.com>
  11 ---
  12  drivers/clk/bcm/clk-cygnus.c | 146 +++++++++++++++++++++----------------------
  13  1 file changed, 73 insertions(+), 73 deletions(-)
  14
  15 --- a/drivers/clk/bcm/clk-cygnus.c
  16 +++ b/drivers/clk/bcm/clk-cygnus.c
  17 @@ -23,28 +23,28 @@
  18  #include <dt-bindings/clock/bcm-cygnus.h>
  19  #include "clk-iproc.h"
  20
  21 -#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
  22 +#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
  23
  24 -#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
  25 +#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
  26         .pwr_shift = ps, .iso_shift = is }
  27
  28 -#define sw_ctrl_val(o, s) { .offset = o, .shift = s, }
  29 +#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
  30
  31 -#define asiu_div_val(o, es, hs, hw, ls, lw) \
  32 +#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
  33                 { .offset = o, .en_shift = es, .high_shift = hs, \
  34                 .high_width = hw, .low_shift = ls, .low_width = lw }
  35
  36 -#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
  37 +#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
  38         .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
  39         .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
  40         .ka_width = kaw }
  41
  42 -#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo }
  43 +#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
  44
  45 -#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
  46 +#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
  47         .hold_shift = hs, .bypass_shift = bs }
  48
  49 -#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
  50 +#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }
  51
  52  static void __init cygnus_armpll_init(struct device_node *node)
  53  {
  54 @@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygn
  55  static const struct iproc_pll_ctrl genpll = {
  56         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
  57                 IPROC_CLK_PLL_NEEDS_SW_CFG,
  58 -       .aon = aon_val(0x0, 2, 1, 0),
  59 -       .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
  60 -       .sw_ctrl = sw_ctrl_val(0x10, 31),
  61 -       .ndiv_int = reg_val(0x10, 20, 10),
  62 -       .ndiv_frac = reg_val(0x10, 0, 20),
  63 -       .pdiv = reg_val(0x14, 0, 4),
  64 -       .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
  65 -       .status = reg_val(0x28, 12, 1),
  66 +       .aon = AON_VAL(0x0, 2, 1, 0),
  67 +       .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
  68 +       .sw_ctrl = SW_CTRL_VAL(0x10, 31),
  69 +       .ndiv_int = REG_VAL(0x10, 20, 10),
  70 +       .ndiv_frac = REG_VAL(0x10, 0, 20),
  71 +       .pdiv = REG_VAL(0x14, 0, 4),
  72 +       .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
  73 +       .status = REG_VAL(0x28, 12, 1),
  74  };
  75
  76  static const struct iproc_clk_ctrl genpll_clk[] = {
  77         [BCM_CYGNUS_GENPLL_AXI21_CLK] = {
  78                 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
  79                 .flags = IPROC_CLK_AON,
  80 -               .enable = enable_val(0x4, 6, 0, 12),
  81 -               .mdiv = reg_val(0x20, 0, 8),
  82 +               .enable = ENABLE_VAL(0x4, 6, 0, 12),
  83 +               .mdiv = REG_VAL(0x20, 0, 8),
  84         },
  85         [BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
  86                 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
  87                 .flags = IPROC_CLK_AON,
  88 -               .enable = enable_val(0x4, 7, 1, 13),
  89 -               .mdiv = reg_val(0x20, 10, 8),
  90 +               .enable = ENABLE_VAL(0x4, 7, 1, 13),
  91 +               .mdiv = REG_VAL(0x20, 10, 8),
  92         },
  93         [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
  94                 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
  95                 .flags = IPROC_CLK_AON,
  96 -               .enable = enable_val(0x4, 8, 2, 14),
  97 -               .mdiv = reg_val(0x20, 20, 8),
  98 +               .enable = ENABLE_VAL(0x4, 8, 2, 14),
  99 +               .mdiv = REG_VAL(0x20, 20, 8),
 100         },
 101         [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
 102                 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
 103                 .flags = IPROC_CLK_AON,
 104 -               .enable = enable_val(0x4, 9, 3, 15),
 105 -               .mdiv = reg_val(0x24, 0, 8),
 106 +               .enable = ENABLE_VAL(0x4, 9, 3, 15),
 107 +               .mdiv = REG_VAL(0x24, 0, 8),
 108         },
 109         [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
 110                 .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
 111                 .flags = IPROC_CLK_AON,
 112 -               .enable = enable_val(0x4, 10, 4, 16),
 113 -               .mdiv = reg_val(0x24, 10, 8),
 114 +               .enable = ENABLE_VAL(0x4, 10, 4, 16),
 115 +               .mdiv = REG_VAL(0x24, 10, 8),
 116         },
 117         [BCM_CYGNUS_GENPLL_CAN_CLK] = {
 118                 .channel = BCM_CYGNUS_GENPLL_CAN_CLK,
 119                 .flags = IPROC_CLK_AON,
 120 -               .enable = enable_val(0x4, 11, 5, 17),
 121 -               .mdiv = reg_val(0x24, 20, 8),
 122 +               .enable = ENABLE_VAL(0x4, 11, 5, 17),
 123 +               .mdiv = REG_VAL(0x24, 20, 8),
 124         },
 125  };
 126
 127 @@ -113,51 +113,51 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn
 128
 129  static const struct iproc_pll_ctrl lcpll0 = {
 130         .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
 131 -       .aon = aon_val(0x0, 2, 5, 4),
 132 -       .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
 133 -       .sw_ctrl = sw_ctrl_val(0x4, 31),
 134 -       .ndiv_int = reg_val(0x4, 16, 10),
 135 -       .pdiv = reg_val(0x4, 26, 4),
 136 -       .vco_ctrl = vco_ctrl_val(0x10, 0x14),
 137 -       .status = reg_val(0x18, 12, 1),
 138 +       .aon = AON_VAL(0x0, 2, 5, 4),
 139 +       .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
 140 +       .sw_ctrl = SW_CTRL_VAL(0x4, 31),
 141 +       .ndiv_int = REG_VAL(0x4, 16, 10),
 142 +       .pdiv = REG_VAL(0x4, 26, 4),
 143 +       .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14),
 144 +       .status = REG_VAL(0x18, 12, 1),
 145  };
 146
 147  static const struct iproc_clk_ctrl lcpll0_clk[] = {
 148         [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = {
 149                 .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
 150                 .flags = IPROC_CLK_AON,
 151 -               .enable = enable_val(0x0, 7, 1, 13),
 152 -               .mdiv = reg_val(0x8, 0, 8),
 153 +               .enable = ENABLE_VAL(0x0, 7, 1, 13),
 154 +               .mdiv = REG_VAL(0x8, 0, 8),
 155         },
 156         [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = {
 157                 .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
 158                 .flags = IPROC_CLK_AON,
 159 -               .enable = enable_val(0x0, 8, 2, 14),
 160 -               .mdiv = reg_val(0x8, 10, 8),
 161 +               .enable = ENABLE_VAL(0x0, 8, 2, 14),
 162 +               .mdiv = REG_VAL(0x8, 10, 8),
 163         },
 164         [BCM_CYGNUS_LCPLL0_SDIO_CLK] = {
 165                 .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
 166                 .flags = IPROC_CLK_AON,
 167 -               .enable = enable_val(0x0, 9, 3, 15),
 168 -               .mdiv = reg_val(0x8, 20, 8),
 169 +               .enable = ENABLE_VAL(0x0, 9, 3, 15),
 170 +               .mdiv = REG_VAL(0x8, 20, 8),
 171         },
 172         [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = {
 173                 .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
 174                 .flags = IPROC_CLK_AON,
 175 -               .enable = enable_val(0x0, 10, 4, 16),
 176 -               .mdiv = reg_val(0xc, 0, 8),
 177 +               .enable = ENABLE_VAL(0x0, 10, 4, 16),
 178 +               .mdiv = REG_VAL(0xc, 0, 8),
 179         },
 180         [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = {
 181                 .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
 182                 .flags = IPROC_CLK_AON,
 183 -               .enable = enable_val(0x0, 11, 5, 17),
 184 -               .mdiv = reg_val(0xc, 10, 8),
 185 +               .enable = ENABLE_VAL(0x0, 11, 5, 17),
 186 +               .mdiv = REG_VAL(0xc, 10, 8),
 187         },
 188         [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = {
 189                 .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
 190                 .flags = IPROC_CLK_AON,
 191 -               .enable = enable_val(0x0, 12, 6, 18),
 192 -               .mdiv = reg_val(0xc, 20, 8),
 193 +               .enable = ENABLE_VAL(0x0, 12, 6, 18),
 194 +               .mdiv = REG_VAL(0xc, 20, 8),
 195         },
 196  };
 197
 198 @@ -189,52 +189,52 @@ static const struct iproc_pll_vco_param
 199  static const struct iproc_pll_ctrl mipipll = {
 200         .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC |
 201                  IPROC_CLK_NEEDS_READ_BACK,
 202 -       .aon = aon_val(0x0, 4, 17, 16),
 203 -       .asiu = asiu_gate_val(0x0, 3),
 204 -       .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
 205 -       .ndiv_int = reg_val(0x10, 20, 10),
 206 -       .ndiv_frac = reg_val(0x10, 0, 20),
 207 -       .pdiv = reg_val(0x14, 0, 4),
 208 -       .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
 209 -       .status = reg_val(0x28, 12, 1),
 210 +       .aon = AON_VAL(0x0, 4, 17, 16),
 211 +       .asiu = ASIU_GATE_VAL(0x0, 3),
 212 +       .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
 213 +       .ndiv_int = REG_VAL(0x10, 20, 10),
 214 +       .ndiv_frac = REG_VAL(0x10, 0, 20),
 215 +       .pdiv = REG_VAL(0x14, 0, 4),
 216 +       .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
 217 +       .status = REG_VAL(0x28, 12, 1),
 218  };
 219
 220  static const struct iproc_clk_ctrl mipipll_clk[] = {
 221         [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
 222                 .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
 223                 .flags = IPROC_CLK_NEEDS_READ_BACK,
 224 -               .enable = enable_val(0x4, 12, 6, 18),
 225 -               .mdiv = reg_val(0x20, 0, 8),
 226 +               .enable = ENABLE_VAL(0x4, 12, 6, 18),
 227 +               .mdiv = REG_VAL(0x20, 0, 8),
 228         },
 229         [BCM_CYGNUS_MIPIPLL_CH1_LCD] = {
 230                 .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
 231                 .flags = IPROC_CLK_NEEDS_READ_BACK,
 232 -               .enable = enable_val(0x4, 13, 7, 19),
 233 -               .mdiv = reg_val(0x20, 10, 8),
 234 +               .enable = ENABLE_VAL(0x4, 13, 7, 19),
 235 +               .mdiv = REG_VAL(0x20, 10, 8),
 236         },
 237         [BCM_CYGNUS_MIPIPLL_CH2_V3D] = {
 238                 .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
 239                 .flags = IPROC_CLK_NEEDS_READ_BACK,
 240 -               .enable = enable_val(0x4, 14, 8, 20),
 241 -               .mdiv = reg_val(0x20, 20, 8),
 242 +               .enable = ENABLE_VAL(0x4, 14, 8, 20),
 243 +               .mdiv = REG_VAL(0x20, 20, 8),
 244         },
 245         [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = {
 246                 .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
 247                 .flags = IPROC_CLK_NEEDS_READ_BACK,
 248 -               .enable = enable_val(0x4, 15, 9, 21),
 249 -               .mdiv = reg_val(0x24, 0, 8),
 250 +               .enable = ENABLE_VAL(0x4, 15, 9, 21),
 251 +               .mdiv = REG_VAL(0x24, 0, 8),
 252         },
 253         [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = {
 254                 .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
 255                 .flags = IPROC_CLK_NEEDS_READ_BACK,
 256 -               .enable = enable_val(0x4, 16, 10, 22),
 257 -               .mdiv = reg_val(0x24, 10, 8),
 258 +               .enable = ENABLE_VAL(0x4, 16, 10, 22),
 259 +               .mdiv = REG_VAL(0x24, 10, 8),
 260         },
 261         [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = {
 262                 .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
 263                 .flags = IPROC_CLK_NEEDS_READ_BACK,
 264 -               .enable = enable_val(0x4, 17, 11, 23),
 265 -               .mdiv = reg_val(0x24, 20, 8),
 266 +               .enable = ENABLE_VAL(0x4, 17, 11, 23),
 267 +               .mdiv = REG_VAL(0x24, 20, 8),
 268         },
 269  };
 270
 271 @@ -247,15 +247,15 @@ static void __init cygnus_mipipll_clk_in
 272  CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
 273
 274  static const struct iproc_asiu_div asiu_div[] = {
 275 -       [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_div_val(0x0, 31, 16, 10, 0, 10),
 276 -       [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_div_val(0x4, 31, 16, 10, 0, 10),
 277 -       [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_div_val(0x8, 31, 16, 10, 0, 10),
 278 +       [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10),
 279 +       [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10),
 280 +       [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10),
 281  };
 282
 283  static const struct iproc_asiu_gate asiu_gate[] = {
 284 -       [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_gate_val(0x0, 7),
 285 -       [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_gate_val(0x0, 9),
 286 -       [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0),
 287 +       [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7),
 288 +       [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9),
 289 +       [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0),
 290  };
 291
 292  static void __init cygnus_asiu_init(struct device_node *node)