target/linux/bcm53xx/patches-4.1/074-ARM-l2c-avoid-passing-auxiliary-control-register-thr.patch

   1 From 5b290ec2074c68b9f4f8f8789fa9b3e1782869e7 Mon Sep 17 00:00:00 2001
   2 From: Russell King <rmk+kernel@arm.linux.org.uk>
   3 Date: Fri, 15 May 2015 12:03:29 +0100
   4 Subject: [PATCH 74/74] ARM: l2c: avoid passing auxiliary control register
   5  through enable method
   6
   7 Avoid passing the auxiliary control register value through the enable
   8 method.  In the resume path, we have to read the value stored in
   9 l2x0_saved_regs.aux_ctrl, only to have it immediately written back by
  10 l2c_enable().  We can avoid this if we have __l2c_init() save the value
  11 directly to l2x0_saved_regs.aux_ctrl before calling the specific enable
  12 method.
  13
  14 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
  15 ---
  16  arch/arm/mm/cache-l2x0.c | 32 +++++++++++++++++---------------
  17  1 file changed, 17 insertions(+), 15 deletions(-)
  18
  19 --- a/arch/arm/mm/cache-l2x0.c
  20 +++ b/arch/arm/mm/cache-l2x0.c
  21 @@ -38,7 +38,7 @@ struct l2c_init_data {
  22         unsigned way_size_0;
  23         unsigned num_lock;
  24         void (*of_parse)(const struct device_node *, u32 *, u32 *);
  25 -       void (*enable)(void __iomem *, u32, unsigned);
  26 +       void (*enable)(void __iomem *, unsigned);
  27         void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
  28         void (*save)(void __iomem *);
  29         void (*configure)(void __iomem *);
  30 @@ -118,12 +118,10 @@ static void l2c_configure(void __iomem *
  31   * Enable the L2 cache controller.  This function must only be
  32   * called when the cache controller is known to be disabled.
  33   */
  34 -static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock)
  35 +static void l2c_enable(void __iomem *base, unsigned num_lock)
  36  {
  37         unsigned long flags;
  38
  39 -       l2x0_saved_regs.aux_ctrl = aux;
  40 -
  41         if (outer_cache.configure)
  42                 outer_cache.configure(&l2x0_saved_regs);
  43         else
  44 @@ -160,7 +158,7 @@ static void l2c_resume(void)
  45
  46         /* Do not touch the controller if already enabled. */
  47         if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
  48 -               l2c_enable(base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock);
  49 +               l2c_enable(base, l2x0_data->num_lock);
  50  }
  51
  52  /*
  53 @@ -390,16 +388,16 @@ static void l2c220_sync(void)
  54         raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  55  }
  56
  57 -static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock)
  58 +static void l2c220_enable(void __iomem *base, unsigned num_lock)
  59  {
  60         /*
  61          * Always enable non-secure access to the lockdown registers -
  62          * we write to them as part of the L2C enable sequence so they
  63          * need to be accessible.
  64          */
  65 -       aux |= L220_AUX_CTRL_NS_LOCKDOWN;
  66 +       l2x0_saved_regs.aux_ctrl |= L220_AUX_CTRL_NS_LOCKDOWN;
  67
  68 -       l2c_enable(base, aux, num_lock);
  69 +       l2c_enable(base, num_lock);
  70  }
  71
  72  static void l2c220_unlock(void __iomem *base, unsigned num_lock)
  73 @@ -612,10 +610,11 @@ static int l2c310_cpu_enable_flz(struct
  74         return NOTIFY_OK;
  75  }
  76
  77 -static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
  78 +static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
  79  {
  80         unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK;
  81         bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9;
  82 +       u32 aux = l2x0_saved_regs.aux_ctrl;
  83
  84         if (rev >= L310_CACHE_ID_RTL_R2P0) {
  85                 if (cortex_a9) {
  86 @@ -658,9 +657,9 @@ static void __init l2c310_enable(void __
  87          * we write to them as part of the L2C enable sequence so they
  88          * need to be accessible.
  89          */
  90 -       aux |= L310_AUX_CTRL_NS_LOCKDOWN;
  91 +       l2x0_saved_regs.aux_ctrl = aux | L310_AUX_CTRL_NS_LOCKDOWN;
  92
  93 -       l2c_enable(base, aux, num_lock);
  94 +       l2c_enable(base, num_lock);
  95
  96         /* Read back resulting AUX_CTRL value as it could have been altered. */
  97         aux = readl_relaxed(base + L2X0_AUX_CTRL);
  98 @@ -872,8 +871,11 @@ static int __init __l2c_init(const struc
  99          * Check if l2x0 controller is already enabled.  If we are booting
 100          * in non-secure mode accessing the below registers will fault.
 101          */
 102 -       if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
 103 -               data->enable(l2x0_base, aux, data->num_lock);
 104 +       if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
 105 +               l2x0_saved_regs.aux_ctrl = aux;
 106 +
 107 +               data->enable(l2x0_base, data->num_lock);
 108 +       }
 109
 110         outer_cache = fns;
 111
 112 @@ -1388,7 +1390,7 @@ static void aurora_save(void __iomem *ba
 113   * For Aurora cache in no outer mode, enable via the CP15 coprocessor
 114   * broadcasting of cache commands to L2.
 115   */
 116 -static void __init aurora_enable_no_outer(void __iomem *base, u32 aux,
 117 +static void __init aurora_enable_no_outer(void __iomem *base,
 118         unsigned num_lock)
 119  {
 120         u32 u;
 121 @@ -1399,7 +1401,7 @@ static void __init aurora_enable_no_oute
 122
 123         isb();
 124
 125 -       l2c_enable(base, aux, num_lock);
 126 +       l2c_enable(base, num_lock);
 127  }
 128
 129  static void __init aurora_fixup(void __iomem *base, u32 cache_id,