target/linux/bcm53xx/patches-4.1/040-0004-PCI-iproc-Add-iProc-PCIe-MSI-support.patch

   1 From 3bc2b2348835f6edd33c383a2fbcf15fe3dac3b2 Mon Sep 17 00:00:00 2001
   2 From: Ray Jui <rjui@broadcom.com>
   3 Date: Wed, 6 Jan 2016 18:04:35 -0600
   4 Subject: [PATCH 4/5] PCI: iproc: Add iProc PCIe MSI support
   5
   6 Add PCIe MSI support for both PAXB and PAXC interfaces on all iProc-based
   7 platforms.
   8
   9 The iProc PCIe MSI support deploys an event queue-based implementation.
  10 Each event queue is serviced by a GIC interrupt and can support up to 64
  11 MSI vectors.  Host memory is allocated for the event queues, and each event
  12 queue consists of 64 word-sized entries.  MSI data is written to the lower
  13 16-bit of each entry, whereas the upper 16-bit of the entry is reserved for
  14 the controller for internal processing.
  15
  16 Each event queue is tracked by a head pointer and tail pointer.  Head
  17 pointer indicates the next entry in the event queue to be processed by
  18 the driver and is updated by the driver after processing is done.
  19 The controller uses the tail pointer as the next MSI data insertion
  20 point.  The controller ensures MSI data is flushed to host memory before
  21 updating the tail pointer and then triggering the interrupt.
  22
  23 MSI IRQ affinity is supported by evenly distributing the interrupts to each
  24 CPU core.  MSI vector is moved from one GIC interrupt to another in order
  25 to steer to the target CPU.
  26
  27 Therefore, the actual number of supported MSI vectors is:
  28
  29   M * 64 / N
  30
  31 where M denotes the number of GIC interrupts (event queues), and N denotes
  32 the number of CPU cores.
  33
  34 This iProc event queue-based MSI support should not be used with newer
  35 platforms with integrated MSI support in the GIC (e.g., giv2m or
  36 gicv3-its).
  37
  38 [bhelgaas: fold in Kconfig fixes from Arnd Bergmann <arnd@arndb.de>]
  39 Signed-off-by: Ray Jui <rjui@broadcom.com>
  40 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  41 Reviewed-by: Anup Patel <anup.patel@broadcom.com>
  42 Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
  43 Reviewed-by: Scott Branden <sbranden@broadcom.com>
  44 Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
  45 ---
  46  drivers/pci/host/Kconfig               |  10 +
  47  drivers/pci/host/Makefile              |   1 +
  48  drivers/pci/host/pcie-iproc-bcma.c     |   1 +
  49  drivers/pci/host/pcie-iproc-msi.c      | 675 +++++++++++++++++++++++++++++++++
  50  drivers/pci/host/pcie-iproc-platform.c |   1 +
  51  drivers/pci/host/pcie-iproc.c          |  26 ++
  52  drivers/pci/host/pcie-iproc.h          |  23 +-
  53  7 files changed, 735 insertions(+), 2 deletions(-)
  54  create mode 100644 drivers/pci/host/pcie-iproc-msi.c
  55
  56 --- a/drivers/pci/host/Kconfig
  57 +++ b/drivers/pci/host/Kconfig
  58 @@ -133,5 +133,15 @@ config PCIE_IPROC_BCMA
  59         help
  60           Say Y here if you want to use the Broadcom iProc PCIe controller
  61           through the BCMA bus interface
  62 +
  63 +config PCIE_IPROC_MSI
  64 +       bool "Broadcom iProc PCIe MSI support"
  65 +       depends on PCIE_IPROC_PLATFORM || PCIE_IPROC_BCMA
  66 +       depends on PCI_MSI
  67 +       select PCI_MSI_IRQ_DOMAIN
  68 +       default ARCH_BCM_IPROC
  69 +       help
  70 +         Say Y here if you want to enable MSI support for Broadcom's iProc
  71 +         PCIe controller
  72
  73  endmenu
  74 --- a/drivers/pci/host/Makefile
  75 +++ b/drivers/pci/host/Makefile
  76 @@ -14,5 +14,6 @@ obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
  77  obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
  78  obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
  79  obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
  80 +obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
  81  obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
  82  obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
  83 --- a/drivers/pci/host/pcie-iproc-bcma.c
  84 +++ b/drivers/pci/host/pcie-iproc-bcma.c
  85 @@ -55,6 +55,7 @@ static int iproc_pcie_bcma_probe(struct
  86         bcma_set_drvdata(bdev, pcie);
  87
  88         pcie->base = bdev->io_addr;
  89 +       pcie->base_addr = bdev->addr;
  90
  91         res_mem.start = bdev->addr_s[0];
  92         res_mem.end = bdev->addr_s[0] + SZ_128M - 1;
  93 --- /dev/null
  94 +++ b/drivers/pci/host/pcie-iproc-msi.c
  95 @@ -0,0 +1,675 @@
  96 +/*
  97 + * Copyright (C) 2015 Broadcom Corporation
  98 + *
  99 + * This program is free software; you can redistribute it and/or
 100 + * modify it under the terms of the GNU General Public License as
 101 + * published by the Free Software Foundation version 2.
 102 + *
 103 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 104 + * kind, whether express or implied; without even the implied warranty
 105 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 106 + * GNU General Public License for more details.
 107 + */
 108 +
 109 +#include <linux/interrupt.h>
 110 +#include <linux/irqchip/chained_irq.h>
 111 +#include <linux/irqdomain.h>
 112 +#include <linux/msi.h>
 113 +#include <linux/of_irq.h>
 114 +#include <linux/of_pci.h>
 115 +#include <linux/pci.h>
 116 +
 117 +#include "pcie-iproc.h"
 118 +
 119 +#define IPROC_MSI_INTR_EN_SHIFT        11
 120 +#define IPROC_MSI_INTR_EN              BIT(IPROC_MSI_INTR_EN_SHIFT)
 121 +#define IPROC_MSI_INT_N_EVENT_SHIFT    1
 122 +#define IPROC_MSI_INT_N_EVENT          BIT(IPROC_MSI_INT_N_EVENT_SHIFT)
 123 +#define IPROC_MSI_EQ_EN_SHIFT          0
 124 +#define IPROC_MSI_EQ_EN                BIT(IPROC_MSI_EQ_EN_SHIFT)
 125 +
 126 +#define IPROC_MSI_EQ_MASK              0x3f
 127 +
 128 +/* Max number of GIC interrupts */
 129 +#define NR_HW_IRQS                     6
 130 +
 131 +/* Number of entries in each event queue */
 132 +#define EQ_LEN                         64
 133 +
 134 +/* Size of each event queue memory region */
 135 +#define EQ_MEM_REGION_SIZE             SZ_4K
 136 +
 137 +/* Size of each MSI address region */
 138 +#define MSI_MEM_REGION_SIZE            SZ_4K
 139 +
 140 +enum iproc_msi_reg {
 141 +       IPROC_MSI_EQ_PAGE = 0,
 142 +       IPROC_MSI_EQ_PAGE_UPPER,
 143 +       IPROC_MSI_PAGE,
 144 +       IPROC_MSI_PAGE_UPPER,
 145 +       IPROC_MSI_CTRL,
 146 +       IPROC_MSI_EQ_HEAD,
 147 +       IPROC_MSI_EQ_TAIL,
 148 +       IPROC_MSI_INTS_EN,
 149 +       IPROC_MSI_REG_SIZE,
 150 +};
 151 +
 152 +struct iproc_msi;
 153 +
 154 +/**
 155 + * iProc MSI group
 156 + *
 157 + * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
 158 + * event queue.
 159 + *
 160 + * @msi: pointer to iProc MSI data
 161 + * @gic_irq: GIC interrupt
 162 + * @eq: Event queue number
 163 + */
 164 +struct iproc_msi_grp {
 165 +       struct iproc_msi *msi;
 166 +       int gic_irq;
 167 +       unsigned int eq;
 168 +};
 169 +
 170 +/**
 171 + * iProc event queue based MSI
 172 + *
 173 + * Only meant to be used on platforms without MSI support integrated into the
 174 + * GIC.
 175 + *
 176 + * @pcie: pointer to iProc PCIe data
 177 + * @reg_offsets: MSI register offsets
 178 + * @grps: MSI groups
 179 + * @nr_irqs: number of total interrupts connected to GIC
 180 + * @nr_cpus: number of toal CPUs
 181 + * @has_inten_reg: indicates the MSI interrupt enable register needs to be
 182 + * set explicitly (required for some legacy platforms)
 183 + * @bitmap: MSI vector bitmap
 184 + * @bitmap_lock: lock to protect access to the MSI bitmap
 185 + * @nr_msi_vecs: total number of MSI vectors
 186 + * @inner_domain: inner IRQ domain
 187 + * @msi_domain: MSI IRQ domain
 188 + * @nr_eq_region: required number of 4K aligned memory region for MSI event
 189 + * queues
 190 + * @nr_msi_region: required number of 4K aligned address region for MSI posted
 191 + * writes
 192 + * @eq_cpu: pointer to allocated memory region for MSI event queues
 193 + * @eq_dma: DMA address of MSI event queues
 194 + * @msi_addr: MSI address
 195 + */
 196 +struct iproc_msi {
 197 +       struct iproc_pcie *pcie;
 198 +       const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];
 199 +       struct iproc_msi_grp *grps;
 200 +       int nr_irqs;
 201 +       int nr_cpus;
 202 +       bool has_inten_reg;
 203 +       unsigned long *bitmap;
 204 +       struct mutex bitmap_lock;
 205 +       unsigned int nr_msi_vecs;
 206 +       struct irq_domain *inner_domain;
 207 +       struct irq_domain *msi_domain;
 208 +       unsigned int nr_eq_region;
 209 +       unsigned int nr_msi_region;
 210 +       void *eq_cpu;
 211 +       dma_addr_t eq_dma;
 212 +       phys_addr_t msi_addr;
 213 +};
 214 +
 215 +static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
 216 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
 217 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
 218 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
 219 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
 220 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
 221 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
 222 +};
 223 +
 224 +static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
 225 +       { 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
 226 +       { 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 },
 227 +       { 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 },
 228 +       { 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c },
 229 +};
 230 +
 231 +static inline u32 iproc_msi_read_reg(struct iproc_msi *msi,
 232 +                                    enum iproc_msi_reg reg,
 233 +                                    unsigned int eq)
 234 +{
 235 +       struct iproc_pcie *pcie = msi->pcie;
 236 +
 237 +       return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);
 238 +}
 239 +
 240 +static inline void iproc_msi_write_reg(struct iproc_msi *msi,
 241 +                                      enum iproc_msi_reg reg,
 242 +                                      int eq, u32 val)
 243 +{
 244 +       struct iproc_pcie *pcie = msi->pcie;
 245 +
 246 +       writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
 247 +}
 248 +
 249 +static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq)
 250 +{
 251 +       return (hwirq % msi->nr_irqs);
 252 +}
 253 +
 254 +static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi,
 255 +                                                unsigned long hwirq)
 256 +{
 257 +       if (msi->nr_msi_region > 1)
 258 +               return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
 259 +       else
 260 +               return hwirq_to_group(msi, hwirq) * sizeof(u32);
 261 +}
 262 +
 263 +static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq)
 264 +{
 265 +       if (msi->nr_eq_region > 1)
 266 +               return eq * EQ_MEM_REGION_SIZE;
 267 +       else
 268 +               return eq * EQ_LEN * sizeof(u32);
 269 +}
 270 +
 271 +static struct irq_chip iproc_msi_irq_chip = {
 272 +       .name = "iProc-MSI",
 273 +};
 274 +
 275 +static struct msi_domain_info iproc_msi_domain_info = {
 276 +       .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 277 +               MSI_FLAG_PCI_MSIX,
 278 +       .chip = &iproc_msi_irq_chip,
 279 +};
 280 +
 281 +/*
 282 + * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
 283 + * dedicated event queue.  Each MSI group can support up to 64 MSI vectors.
 284 + *
 285 + * The number of MSI groups varies between different iProc SoCs.  The total
 286 + * number of CPU cores also varies.  To support MSI IRQ affinity, we
 287 + * distribute GIC interrupts across all available CPUs.  MSI vector is moved
 288 + * from one GIC interrupt to another to steer to the target CPU.
 289 + *
 290 + * Assuming:
 291 + * - the number of MSI groups is M
 292 + * - the number of CPU cores is N
 293 + * - M is always a multiple of N
 294 + *
 295 + * Total number of raw MSI vectors = M * 64
 296 + * Total number of supported MSI vectors = (M * 64) / N
 297 + */
 298 +static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq)
 299 +{
 300 +       return (hwirq % msi->nr_cpus);
 301 +}
 302 +
 303 +static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi,
 304 +                                                    unsigned long hwirq)
 305 +{
 306 +       return (hwirq - hwirq_to_cpu(msi, hwirq));
 307 +}
 308 +
 309 +static int iproc_msi_irq_set_affinity(struct irq_data *data,
 310 +                                     const struct cpumask *mask, bool force)
 311 +{
 312 +       struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
 313 +       int target_cpu = cpumask_first(mask);
 314 +       int curr_cpu;
 315 +
 316 +       curr_cpu = hwirq_to_cpu(msi, data->hwirq);
 317 +       if (curr_cpu == target_cpu)
 318 +               return IRQ_SET_MASK_OK_DONE;
 319 +
 320 +       /* steer MSI to the target CPU */
 321 +       data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
 322 +
 323 +       return IRQ_SET_MASK_OK;
 324 +}
 325 +
 326 +static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
 327 +                                         struct msi_msg *msg)
 328 +{
 329 +       struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
 330 +       dma_addr_t addr;
 331 +
 332 +       addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq);
 333 +       msg->address_lo = lower_32_bits(addr);
 334 +       msg->address_hi = upper_32_bits(addr);
 335 +       msg->data = data->hwirq;
 336 +}
 337 +
 338 +static struct irq_chip iproc_msi_bottom_irq_chip = {
 339 +       .name = "MSI",
 340 +       .irq_set_affinity = iproc_msi_irq_set_affinity,
 341 +       .irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg,
 342 +};
 343 +
 344 +static int iproc_msi_irq_domain_alloc(struct irq_domain *domain,
 345 +                                     unsigned int virq, unsigned int nr_irqs,
 346 +                                     void *args)
 347 +{
 348 +       struct iproc_msi *msi = domain->host_data;
 349 +       int hwirq;
 350 +
 351 +       mutex_lock(&msi->bitmap_lock);
 352 +
 353 +       /* Allocate 'nr_cpus' number of MSI vectors each time */
 354 +       hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0,
 355 +                                          msi->nr_cpus, 0);
 356 +       if (hwirq < msi->nr_msi_vecs) {
 357 +               bitmap_set(msi->bitmap, hwirq, msi->nr_cpus);
 358 +       } else {
 359 +               mutex_unlock(&msi->bitmap_lock);
 360 +               return -ENOSPC;
 361 +       }
 362 +
 363 +       mutex_unlock(&msi->bitmap_lock);
 364 +
 365 +       irq_domain_set_info(domain, virq, hwirq, &iproc_msi_bottom_irq_chip,
 366 +                           domain->host_data, handle_simple_irq, NULL, NULL);
 367 +
 368 +       return 0;
 369 +}
 370 +
 371 +static void iproc_msi_irq_domain_free(struct irq_domain *domain,
 372 +                                     unsigned int virq, unsigned int nr_irqs)
 373 +{
 374 +       struct irq_data *data = irq_domain_get_irq_data(domain, virq);
 375 +       struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
 376 +       unsigned int hwirq;
 377 +
 378 +       mutex_lock(&msi->bitmap_lock);
 379 +
 380 +       hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq);
 381 +       bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus);
 382 +
 383 +       mutex_unlock(&msi->bitmap_lock);
 384 +
 385 +       irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 386 +}
 387 +
 388 +static const struct irq_domain_ops msi_domain_ops = {
 389 +       .alloc = iproc_msi_irq_domain_alloc,
 390 +       .free = iproc_msi_irq_domain_free,
 391 +};
 392 +
 393 +static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head)
 394 +{
 395 +       u32 *msg, hwirq;
 396 +       unsigned int offs;
 397 +
 398 +       offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32);
 399 +       msg = (u32 *)(msi->eq_cpu + offs);
 400 +       hwirq = *msg & IPROC_MSI_EQ_MASK;
 401 +
 402 +       /*
 403 +        * Since we have multiple hwirq mapped to a single MSI vector,
 404 +        * now we need to derive the hwirq at CPU0.  It can then be used to
 405 +        * mapped back to virq.
 406 +        */
 407 +       return hwirq_to_canonical_hwirq(msi, hwirq);
 408 +}
 409 +
 410 +static void iproc_msi_handler(struct irq_desc *desc)
 411 +{
 412 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 413 +       struct iproc_msi_grp *grp;
 414 +       struct iproc_msi *msi;
 415 +       struct iproc_pcie *pcie;
 416 +       u32 eq, head, tail, nr_events;
 417 +       unsigned long hwirq;
 418 +       int virq;
 419 +
 420 +       chained_irq_enter(chip, desc);
 421 +
 422 +       grp = irq_desc_get_handler_data(desc);
 423 +       msi = grp->msi;
 424 +       pcie = msi->pcie;
 425 +       eq = grp->eq;
 426 +
 427 +       /*
 428 +        * iProc MSI event queue is tracked by head and tail pointers.  Head
 429 +        * pointer indicates the next entry (MSI data) to be consumed by SW in
 430 +        * the queue and needs to be updated by SW.  iProc MSI core uses the
 431 +        * tail pointer as the next data insertion point.
 432 +        *
 433 +        * Entries between head and tail pointers contain valid MSI data.  MSI
 434 +        * data is guaranteed to be in the event queue memory before the tail
 435 +        * pointer is updated by the iProc MSI core.
 436 +        */
 437 +       head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD,
 438 +                                 eq) & IPROC_MSI_EQ_MASK;
 439 +       do {
 440 +               tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL,
 441 +                                         eq) & IPROC_MSI_EQ_MASK;
 442 +
 443 +               /*
 444 +                * Figure out total number of events (MSI data) to be
 445 +                * processed.
 446 +                */
 447 +               nr_events = (tail < head) ?
 448 +                       (EQ_LEN - (head - tail)) : (tail - head);
 449 +               if (!nr_events)
 450 +                       break;
 451 +
 452 +               /* process all outstanding events */
 453 +               while (nr_events--) {
 454 +                       hwirq = decode_msi_hwirq(msi, eq, head);
 455 +                       virq = irq_find_mapping(msi->inner_domain, hwirq);
 456 +                       generic_handle_irq(virq);
 457 +
 458 +                       head++;
 459 +                       head %= EQ_LEN;
 460 +               }
 461 +
 462 +               /*
 463 +                * Now all outstanding events have been processed.  Update the
 464 +                * head pointer.
 465 +                */
 466 +               iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head);
 467 +
 468 +               /*
 469 +                * Now go read the tail pointer again to see if there are new
 470 +                * oustanding events that came in during the above window.
 471 +                */
 472 +       } while (true);
 473 +
 474 +       chained_irq_exit(chip, desc);
 475 +}
 476 +
 477 +static void iproc_msi_enable(struct iproc_msi *msi)
 478 +{
 479 +       int i, eq;
 480 +       u32 val;
 481 +
 482 +       /* Program memory region for each event queue */
 483 +       for (i = 0; i < msi->nr_eq_region; i++) {
 484 +               dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE);
 485 +
 486 +               iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i,
 487 +                                   lower_32_bits(addr));
 488 +               iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i,
 489 +                                   upper_32_bits(addr));
 490 +       }
 491 +
 492 +       /* Program address region for MSI posted writes */
 493 +       for (i = 0; i < msi->nr_msi_region; i++) {
 494 +               phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE);
 495 +
 496 +               iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i,
 497 +                                   lower_32_bits(addr));
 498 +               iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i,
 499 +                                   upper_32_bits(addr));
 500 +       }
 501 +
 502 +       for (eq = 0; eq < msi->nr_irqs; eq++) {
 503 +               /* Enable MSI event queue */
 504 +               val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
 505 +                       IPROC_MSI_EQ_EN;
 506 +               iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
 507 +
 508 +               /*
 509 +                * Some legacy platforms require the MSI interrupt enable
 510 +                * register to be set explicitly.
 511 +                */
 512 +               if (msi->has_inten_reg) {
 513 +                       val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
 514 +                       val |= BIT(eq);
 515 +                       iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
 516 +               }
 517 +       }
 518 +}
 519 +
 520 +static void iproc_msi_disable(struct iproc_msi *msi)
 521 +{
 522 +       u32 eq, val;
 523 +
 524 +       for (eq = 0; eq < msi->nr_irqs; eq++) {
 525 +               if (msi->has_inten_reg) {
 526 +                       val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
 527 +                       val &= ~BIT(eq);
 528 +                       iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
 529 +               }
 530 +
 531 +               val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq);
 532 +               val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
 533 +                        IPROC_MSI_EQ_EN);
 534 +               iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
 535 +       }
 536 +}
 537 +
 538 +static int iproc_msi_alloc_domains(struct device_node *node,
 539 +                                  struct iproc_msi *msi)
 540 +{
 541 +       msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs,
 542 +                                                 &msi_domain_ops, msi);
 543 +       if (!msi->inner_domain)
 544 +               return -ENOMEM;
 545 +
 546 +       msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
 547 +                                                   &iproc_msi_domain_info,
 548 +                                                   msi->inner_domain);
 549 +       if (!msi->msi_domain) {
 550 +               irq_domain_remove(msi->inner_domain);
 551 +               return -ENOMEM;
 552 +       }
 553 +
 554 +       return 0;
 555 +}
 556 +
 557 +static void iproc_msi_free_domains(struct iproc_msi *msi)
 558 +{
 559 +       if (msi->msi_domain)
 560 +               irq_domain_remove(msi->msi_domain);
 561 +
 562 +       if (msi->inner_domain)
 563 +               irq_domain_remove(msi->inner_domain);
 564 +}
 565 +
 566 +static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu)
 567 +{
 568 +       int i;
 569 +
 570 +       for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
 571 +               irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
 572 +                                                NULL, NULL);
 573 +       }
 574 +}
 575 +
 576 +static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu)
 577 +{
 578 +       int i, ret;
 579 +       cpumask_var_t mask;
 580 +       struct iproc_pcie *pcie = msi->pcie;
 581 +
 582 +       for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
 583 +               irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
 584 +                                                iproc_msi_handler,
 585 +                                                &msi->grps[i]);
 586 +               /* Dedicate GIC interrupt to each CPU core */
 587 +               if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
 588 +                       cpumask_clear(mask);
 589 +                       cpumask_set_cpu(cpu, mask);
 590 +                       ret = irq_set_affinity(msi->grps[i].gic_irq, mask);
 591 +                       if (ret)
 592 +                               dev_err(pcie->dev,
 593 +                                       "failed to set affinity for IRQ%d\n",
 594 +                                       msi->grps[i].gic_irq);
 595 +                       free_cpumask_var(mask);
 596 +               } else {
 597 +                       dev_err(pcie->dev, "failed to alloc CPU mask\n");
 598 +                       ret = -EINVAL;
 599 +               }
 600 +
 601 +               if (ret) {
 602 +                       /* Free all configured/unconfigured IRQs */
 603 +                       iproc_msi_irq_free(msi, cpu);
 604 +                       return ret;
 605 +               }
 606 +       }
 607 +
 608 +       return 0;
 609 +}
 610 +
 611 +int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
 612 +{
 613 +       struct iproc_msi *msi;
 614 +       int i, ret;
 615 +       unsigned int cpu;
 616 +
 617 +       if (!of_device_is_compatible(node, "brcm,iproc-msi"))
 618 +               return -ENODEV;
 619 +
 620 +       if (!of_find_property(node, "msi-controller", NULL))
 621 +               return -ENODEV;
 622 +
 623 +       if (pcie->msi)
 624 +               return -EBUSY;
 625 +
 626 +       msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL);
 627 +       if (!msi)
 628 +               return -ENOMEM;
 629 +
 630 +       msi->pcie = pcie;
 631 +       pcie->msi = msi;
 632 +       msi->msi_addr = pcie->base_addr;
 633 +       mutex_init(&msi->bitmap_lock);
 634 +       msi->nr_cpus = num_possible_cpus();
 635 +
 636 +       msi->nr_irqs = of_irq_count(node);
 637 +       if (!msi->nr_irqs) {
 638 +               dev_err(pcie->dev, "found no MSI GIC interrupt\n");
 639 +               return -ENODEV;
 640 +       }
 641 +
 642 +       if (msi->nr_irqs > NR_HW_IRQS) {
 643 +               dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n",
 644 +                        msi->nr_irqs);
 645 +               msi->nr_irqs = NR_HW_IRQS;
 646 +       }
 647 +
 648 +       if (msi->nr_irqs < msi->nr_cpus) {
 649 +               dev_err(pcie->dev,
 650 +                       "not enough GIC interrupts for MSI affinity\n");
 651 +               return -EINVAL;
 652 +       }
 653 +
 654 +       if (msi->nr_irqs % msi->nr_cpus != 0) {
 655 +               msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus;
 656 +               dev_warn(pcie->dev, "Reducing number of interrupts to %d\n",
 657 +                        msi->nr_irqs);
 658 +       }
 659 +
 660 +       switch (pcie->type) {
 661 +       case IPROC_PCIE_PAXB:
 662 +               msi->reg_offsets = iproc_msi_reg_paxb;
 663 +               msi->nr_eq_region = 1;
 664 +               msi->nr_msi_region = 1;
 665 +               break;
 666 +       case IPROC_PCIE_PAXC:
 667 +               msi->reg_offsets = iproc_msi_reg_paxc;
 668 +               msi->nr_eq_region = msi->nr_irqs;
 669 +               msi->nr_msi_region = msi->nr_irqs;
 670 +               break;
 671 +       default:
 672 +               dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
 673 +               return -EINVAL;
 674 +       }
 675 +
 676 +       if (of_find_property(node, "brcm,pcie-msi-inten", NULL))
 677 +               msi->has_inten_reg = true;
 678 +
 679 +       msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN;
 680 +       msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs),
 681 +                                  sizeof(*msi->bitmap), GFP_KERNEL);
 682 +       if (!msi->bitmap)
 683 +               return -ENOMEM;
 684 +
 685 +       msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps),
 686 +                                GFP_KERNEL);
 687 +       if (!msi->grps)
 688 +               return -ENOMEM;
 689 +
 690 +       for (i = 0; i < msi->nr_irqs; i++) {
 691 +               unsigned int irq = irq_of_parse_and_map(node, i);
 692 +
 693 +               if (!irq) {
 694 +                       dev_err(pcie->dev, "unable to parse/map interrupt\n");
 695 +                       ret = -ENODEV;
 696 +                       goto free_irqs;
 697 +               }
 698 +               msi->grps[i].gic_irq = irq;
 699 +               msi->grps[i].msi = msi;
 700 +               msi->grps[i].eq = i;
 701 +       }
 702 +
 703 +       /* Reserve memory for event queue and make sure memories are zeroed */
 704 +       msi->eq_cpu = dma_zalloc_coherent(pcie->dev,
 705 +                                         msi->nr_eq_region * EQ_MEM_REGION_SIZE,
 706 +                                         &msi->eq_dma, GFP_KERNEL);
 707 +       if (!msi->eq_cpu) {
 708 +               ret = -ENOMEM;
 709 +               goto free_irqs;
 710 +       }
 711 +
 712 +       ret = iproc_msi_alloc_domains(node, msi);
 713 +       if (ret) {
 714 +               dev_err(pcie->dev, "failed to create MSI domains\n");
 715 +               goto free_eq_dma;
 716 +       }
 717 +
 718 +       for_each_online_cpu(cpu) {
 719 +               ret = iproc_msi_irq_setup(msi, cpu);
 720 +               if (ret)
 721 +                       goto free_msi_irq;
 722 +       }
 723 +
 724 +       iproc_msi_enable(msi);
 725 +
 726 +       return 0;
 727 +
 728 +free_msi_irq:
 729 +       for_each_online_cpu(cpu)
 730 +               iproc_msi_irq_free(msi, cpu);
 731 +       iproc_msi_free_domains(msi);
 732 +
 733 +free_eq_dma:
 734 +       dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
 735 +                         msi->eq_cpu, msi->eq_dma);
 736 +
 737 +free_irqs:
 738 +       for (i = 0; i < msi->nr_irqs; i++) {
 739 +               if (msi->grps[i].gic_irq)
 740 +                       irq_dispose_mapping(msi->grps[i].gic_irq);
 741 +       }
 742 +       pcie->msi = NULL;
 743 +       return ret;
 744 +}
 745 +EXPORT_SYMBOL(iproc_msi_init);
 746 +
 747 +void iproc_msi_exit(struct iproc_pcie *pcie)
 748 +{
 749 +       struct iproc_msi *msi = pcie->msi;
 750 +       unsigned int i, cpu;
 751 +
 752 +       if (!msi)
 753 +               return;
 754 +
 755 +       iproc_msi_disable(msi);
 756 +
 757 +       for_each_online_cpu(cpu)
 758 +               iproc_msi_irq_free(msi, cpu);
 759 +
 760 +       iproc_msi_free_domains(msi);
 761 +
 762 +       dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
 763 +                         msi->eq_cpu, msi->eq_dma);
 764 +
 765 +       for (i = 0; i < msi->nr_irqs; i++) {
 766 +               if (msi->grps[i].gic_irq)
 767 +                       irq_dispose_mapping(msi->grps[i].gic_irq);
 768 +       }
 769 +}
 770 +EXPORT_SYMBOL(iproc_msi_exit);
 771 --- a/drivers/pci/host/pcie-iproc-platform.c
 772 +++ b/drivers/pci/host/pcie-iproc-platform.c
 773 @@ -71,6 +71,7 @@ static int iproc_pcie_pltfm_probe(struct
 774                 dev_err(pcie->dev, "unable to map controller registers\n");
 775                 return -ENOMEM;
 776         }
 777 +       pcie->base_addr = reg.start;
 778
 779         if (of_property_read_bool(np, "brcm,pcie-ob")) {
 780                 u32 val;
 781 --- a/drivers/pci/host/pcie-iproc.c
 782 +++ b/drivers/pci/host/pcie-iproc.c
 783 @@ -440,6 +440,26 @@ static int iproc_pcie_map_ranges(struct
 784         return 0;
 785  }
 786
 787 +static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
 788 +{
 789 +       struct device_node *msi_node;
 790 +
 791 +       msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
 792 +       if (!msi_node)
 793 +               return -ENODEV;
 794 +
 795 +       /*
 796 +        * If another MSI controller is being used, the call below should fail
 797 +        * but that is okay
 798 +        */
 799 +       return iproc_msi_init(pcie, msi_node);
 800 +}
 801 +
 802 +static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
 803 +{
 804 +       iproc_msi_exit(pcie);
 805 +}
 806 +
 807  int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
 808  {
 809         int ret;
 810 @@ -506,6 +526,10 @@ int iproc_pcie_setup(struct iproc_pcie *
 811
 812         iproc_pcie_enable(pcie);
 813
 814 +       if (IS_ENABLED(CONFIG_PCI_MSI))
 815 +               if (iproc_pcie_msi_enable(pcie))
 816 +                       dev_info(pcie->dev, "not using iProc MSI\n");
 817 +
 818         pci_scan_child_bus(bus);
 819         pci_assign_unassigned_bus_resources(bus);
 820         pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
 821 @@ -530,6 +554,8 @@ int iproc_pcie_remove(struct iproc_pcie
 822         pci_stop_root_bus(pcie->root_bus);
 823         pci_remove_root_bus(pcie->root_bus);
 824
 825 +       iproc_pcie_msi_disable(pcie);
 826 +
 827         phy_power_off(pcie->phy);
 828         phy_exit(pcie->phy);
 829
 830 --- a/drivers/pci/host/pcie-iproc.h
 831 +++ b/drivers/pci/host/pcie-iproc.h
 832 @@ -41,6 +41,8 @@ struct iproc_pcie_ob {
 833         resource_size_t window_size;
 834  };
 835
 836 +struct iproc_msi;
 837 +
 838  /**
 839   * iProc PCIe device
 840   *
 841 @@ -48,19 +50,21 @@ struct iproc_pcie_ob {
 842   * @type: iProc PCIe interface type
 843   * @reg_offsets: register offsets
 844   * @base: PCIe host controller I/O register base
 845 + * @base_addr: PCIe host controller register base physical address
 846   * @sysdata: Per PCI controller data (ARM-specific)
 847   * @root_bus: pointer to root bus
 848   * @phy: optional PHY device that controls the Serdes
 849 - * @irqs: interrupt IDs
 850   * @map_irq: function callback to map interrupts
 851 - * @need_ob_cfg: indidates SW needs to configure the outbound mapping window
 852 + * @need_ob_cfg: indicates SW needs to configure the outbound mapping window
 853   * @ob: outbound mapping parameters
 854 + * @msi: MSI data
 855   */
 856  struct iproc_pcie {
 857         struct device *dev;
 858         enum iproc_pcie_type type;
 859         const u16 *reg_offsets;
 860         void __iomem *base;
 861 +       phys_addr_t base_addr;
 862  #ifdef CONFIG_ARM
 863         struct pci_sys_data sysdata;
 864  #endif
 865 @@ -69,9 +73,24 @@ struct iproc_pcie {
 866         int (*map_irq)(const struct pci_dev *, u8, u8);
 867         bool need_ob_cfg;
 868         struct iproc_pcie_ob ob;
 869 +       struct iproc_msi *msi;
 870  };
 871
 872  int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res);
 873  int iproc_pcie_remove(struct iproc_pcie *pcie);
 874
 875 +#ifdef CONFIG_PCIE_IPROC_MSI
 876 +int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node);
 877 +void iproc_msi_exit(struct iproc_pcie *pcie);
 878 +#else
 879 +static inline int iproc_msi_init(struct iproc_pcie *pcie,
 880 +                                struct device_node *node)
 881 +{
 882 +       return -ENODEV;
 883 +}
 884 +static inline void iproc_msi_exit(struct iproc_pcie *pcie)
 885 +{
 886 +}
 887 +#endif
 888 +
 889  #endif /* _PCIE_IPROC_H */