target/linux/bcm27xx/patches-6.1/950-1072-drm-vc4-crtc-Support-odd-horizontal-timings-on-BCM27.patch

   1 From f9f480b04f1dc280bd4411477f5ee7336361367b Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Tue, 24 Oct 2023 16:20:42 +0100
   4 Subject: [PATCH] drm/vc4: crtc: Support odd horizontal timings on BCM2712
   5
   6 BCM2711 runs pixelvalve at two pixels per clock cycle which results
   7 in an unfortunate limitation that odd horizontal timings are not
   8 possible. This is apparent on the standard DMT mode of 1366x768@60
   9 which cannot be driven with correct timing.
  10
  11 BCM2712 defaults to the same behaviour, but has a mode to support
  12 odd timings. While internally it still runs at two pixels per clock,
  13 setting the PV_VCONTROL_ODD_TIMING bit makes it appear externally
  14 to behave as it is one pixel per clock.
  15
  16 Switching to this mode fixes 1366x768@60 mode, and other custom
  17 resultions with odd horizontal timings.
  18
  19 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  20 ---
  21  drivers/gpu/drm/vc4/vc4_crtc.c | 12 ++++--------
  22  drivers/gpu/drm/vc4/vc4_hdmi.c |  4 ++--
  23  drivers/gpu/drm/vc4/vc4_regs.h |  1 +
  24  3 files changed, 7 insertions(+), 10 deletions(-)
  25
  26 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  27 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  28 @@ -398,12 +398,6 @@ static void vc4_crtc_config_pv(struct dr
  29
  30         vc4_crtc_pixelvalve_reset(crtc);
  31
  32 -       /*
  33 -        * NOTE: The BCM2712 has a H_OTE (Horizontal Odd Timing Enable)
  34 -        * bit that, when set, will allow to specify the timings in
  35 -        * pixels instead of cycles, thus allowing to specify odd
  36 -        * timings.
  37 -        */
  38         CRTC_WRITE(PV_HORZA,
  39                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
  40                                  PV_HORZA_HBP) |
  41 @@ -448,6 +442,7 @@ static void vc4_crtc_config_pv(struct dr
  42                  */
  43                 CRTC_WRITE(PV_V_CONTROL,
  44                            PV_VCONTROL_CONTINUOUS |
  45 +                          (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
  46                            (is_dsi ? PV_VCONTROL_DSI : 0) |
  47                            PV_VCONTROL_INTERLACE |
  48                            (odd_field_first
  49 @@ -459,6 +454,7 @@ static void vc4_crtc_config_pv(struct dr
  50         } else {
  51                 CRTC_WRITE(PV_V_CONTROL,
  52                            PV_VCONTROL_CONTINUOUS |
  53 +                          (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
  54                            (is_dsi ? PV_VCONTROL_DSI : 0));
  55                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
  56         }
  57 @@ -1334,7 +1330,7 @@ const struct vc4_pv_data bcm2712_pv0_dat
  58                 .hvs_output = 0,
  59         },
  60         .fifo_depth = 64,
  61 -       .pixels_per_clock = 2,
  62 +       .pixels_per_clock = 1,
  63         .encoder_types = {
  64                 [0] = VC4_ENCODER_TYPE_HDMI0,
  65         },
  66 @@ -1347,7 +1343,7 @@ const struct vc4_pv_data bcm2712_pv1_dat
  67                 .hvs_output = 1,
  68         },
  69         .fifo_depth = 64,
  70 -       .pixels_per_clock = 2,
  71 +       .pixels_per_clock = 1,
  72         .encoder_types = {
  73                 [0] = VC4_ENCODER_TYPE_HDMI1,
  74         },
  75 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  76 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  77 @@ -3958,7 +3958,7 @@ static const struct vc4_hdmi_variant bcm
  78                 PHY_LANE_2,
  79                 PHY_LANE_CK,
  80         },
  81 -       .unsupported_odd_h_timings      = true,
  82 +       .unsupported_odd_h_timings      = false,
  83         .external_irq_controller        = true,
  84
  85         .init_resources         = vc5_hdmi_init_resources,
  86 @@ -3985,7 +3985,7 @@ static const struct vc4_hdmi_variant bcm
  87                 PHY_LANE_2,
  88                 PHY_LANE_CK,
  89         },
  90 -       .unsupported_odd_h_timings      = true,
  91 +       .unsupported_odd_h_timings      = false,
  92         .external_irq_controller        = true,
  93
  94         .init_resources         = vc5_hdmi_init_resources,
  95 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  96 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  97 @@ -155,6 +155,7 @@
  98  # define PV_CONTROL_EN                         BIT(0)
  99
 100  #define PV_V_CONTROL                           0x04
 101 +# define PV_VCONTROL_ODD_TIMING                        BIT(29)
 102  # define PV_VCONTROL_ODD_DELAY_MASK            VC4_MASK(22, 6)
 103  # define PV_VCONTROL_ODD_DELAY_SHIFT           6
 104  # define PV_VCONTROL_ODD_FIRST                 BIT(5)