target/linux/bcm27xx/patches-6.1/950-0618-media-i2c-imx290-Support-variable-sized-registers.patch

   1 From dbb775e681426042415eb6cf48242c5c980af293 Mon Sep 17 00:00:00 2001
   2 From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   3 Date: Sun, 16 Oct 2022 09:15:11 +0300
   4 Subject: [PATCH] media: i2c: imx290: Support variable-sized registers
   5
   6 Upstream commit e70abe881463.
   7
   8 The IMX290 has registers of different sizes. To simplify the code,
   9 handle this in the read/write functions instead of in the callers by
  10 encoding the register size in the symbolic name macros. All registers
  11 are defined as 8-bit for now, a subsequent change will move to larger
  12 registers where applicable.
  13
  14 Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  15 Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
  16 ---
  17  drivers/media/i2c/imx290.c | 354 +++++++++++++++++++------------------
  18  1 file changed, 181 insertions(+), 173 deletions(-)
  19
  20 --- a/drivers/media/i2c/imx290.c
  21 +++ b/drivers/media/i2c/imx290.c
  22 @@ -22,22 +22,28 @@
  23  #include <media/v4l2-fwnode.h>
  24  #include <media/v4l2-subdev.h>
  25
  26 -#define IMX290_STANDBY 0x3000
  27 -#define IMX290_REGHOLD 0x3001
  28 -#define IMX290_XMSTA 0x3002
  29 -#define IMX290_FR_FDG_SEL 0x3009
  30 -#define IMX290_BLKLEVEL_LOW 0x300a
  31 -#define IMX290_BLKLEVEL_HIGH 0x300b
  32 -#define IMX290_GAIN 0x3014
  33 -#define IMX290_HMAX_LOW 0x301c
  34 -#define IMX290_HMAX_HIGH 0x301d
  35 -#define IMX290_PGCTRL 0x308c
  36 -#define IMX290_PHY_LANE_NUM 0x3407
  37 -#define IMX290_CSI_LANE_MODE 0x3443
  38 -
  39 -#define IMX290_PGCTRL_REGEN BIT(0)
  40 -#define IMX290_PGCTRL_THRU BIT(1)
  41 -#define IMX290_PGCTRL_MODE(n) ((n) << 4)
  42 +#define IMX290_REG_SIZE_SHIFT                          16
  43 +#define IMX290_REG_ADDR_MASK                           0xffff
  44 +#define IMX290_REG_8BIT(n)                             ((1U << IMX290_REG_SIZE_SHIFT) | (n))
  45 +#define IMX290_REG_16BIT(n)                            ((2U << IMX290_REG_SIZE_SHIFT) | (n))
  46 +#define IMX290_REG_24BIT(n)                            ((3U << IMX290_REG_SIZE_SHIFT) | (n))
  47 +
  48 +#define IMX290_STANDBY                                 IMX290_REG_8BIT(0x3000)
  49 +#define IMX290_REGHOLD                                 IMX290_REG_8BIT(0x3001)
  50 +#define IMX290_XMSTA                                   IMX290_REG_8BIT(0x3002)
  51 +#define IMX290_FR_FDG_SEL                              IMX290_REG_8BIT(0x3009)
  52 +#define IMX290_BLKLEVEL_LOW                            IMX290_REG_8BIT(0x300a)
  53 +#define IMX290_BLKLEVEL_HIGH                           IMX290_REG_8BIT(0x300b)
  54 +#define IMX290_GAIN                                    IMX290_REG_8BIT(0x3014)
  55 +#define IMX290_HMAX_LOW                                        IMX290_REG_8BIT(0x301c)
  56 +#define IMX290_HMAX_HIGH                               IMX290_REG_8BIT(0x301d)
  57 +#define IMX290_PGCTRL                                  IMX290_REG_8BIT(0x308c)
  58 +#define IMX290_PHY_LANE_NUM                            IMX290_REG_8BIT(0x3407)
  59 +#define IMX290_CSI_LANE_MODE                           IMX290_REG_8BIT(0x3443)
  60 +
  61 +#define IMX290_PGCTRL_REGEN                            BIT(0)
  62 +#define IMX290_PGCTRL_THRU                             BIT(1)
  63 +#define IMX290_PGCTRL_MODE(n)                          ((n) << 4)
  64
  65  static const char * const imx290_supply_name[] = {
  66         "vdda",
  67 @@ -48,7 +54,7 @@ static const char * const imx290_supply_
  68  #define IMX290_NUM_SUPPLIES ARRAY_SIZE(imx290_supply_name)
  69
  70  struct imx290_regval {
  71 -       u16 reg;
  72 +       u32 reg;
  73         u8 val;
  74  };
  75
  76 @@ -111,163 +117,163 @@ static const char * const imx290_test_pa
  77  };
  78
  79  static const struct imx290_regval imx290_global_init_settings[] = {
  80 -       { 0x3007, 0x00 },
  81 -       { 0x3018, 0x65 },
  82 -       { 0x3019, 0x04 },
  83 -       { 0x301a, 0x00 },
  84 -       { 0x3444, 0x20 },
  85 -       { 0x3445, 0x25 },
  86 -       { 0x303a, 0x0c },
  87 -       { 0x3040, 0x00 },
  88 -       { 0x3041, 0x00 },
  89 -       { 0x303c, 0x00 },
  90 -       { 0x303d, 0x00 },
  91 -       { 0x3042, 0x9c },
  92 -       { 0x3043, 0x07 },
  93 -       { 0x303e, 0x49 },
  94 -       { 0x303f, 0x04 },
  95 -       { 0x304b, 0x0a },
  96 -       { 0x300f, 0x00 },
  97 -       { 0x3010, 0x21 },
  98 -       { 0x3012, 0x64 },
  99 -       { 0x3016, 0x09 },
 100 -       { 0x3070, 0x02 },
 101 -       { 0x3071, 0x11 },
 102 -       { 0x309b, 0x10 },
 103 -       { 0x309c, 0x22 },
 104 -       { 0x30a2, 0x02 },
 105 -       { 0x30a6, 0x20 },
 106 -       { 0x30a8, 0x20 },
 107 -       { 0x30aa, 0x20 },
 108 -       { 0x30ac, 0x20 },
 109 -       { 0x30b0, 0x43 },
 110 -       { 0x3119, 0x9e },
 111 -       { 0x311c, 0x1e },
 112 -       { 0x311e, 0x08 },
 113 -       { 0x3128, 0x05 },
 114 -       { 0x313d, 0x83 },
 115 -       { 0x3150, 0x03 },
 116 -       { 0x317e, 0x00 },
 117 -       { 0x32b8, 0x50 },
 118 -       { 0x32b9, 0x10 },
 119 -       { 0x32ba, 0x00 },
 120 -       { 0x32bb, 0x04 },
 121 -       { 0x32c8, 0x50 },
 122 -       { 0x32c9, 0x10 },
 123 -       { 0x32ca, 0x00 },
 124 -       { 0x32cb, 0x04 },
 125 -       { 0x332c, 0xd3 },
 126 -       { 0x332d, 0x10 },
 127 -       { 0x332e, 0x0d },
 128 -       { 0x3358, 0x06 },
 129 -       { 0x3359, 0xe1 },
 130 -       { 0x335a, 0x11 },
 131 -       { 0x3360, 0x1e },
 132 -       { 0x3361, 0x61 },
 133 -       { 0x3362, 0x10 },
 134 -       { 0x33b0, 0x50 },
 135 -       { 0x33b2, 0x1a },
 136 -       { 0x33b3, 0x04 },
 137 +       { IMX290_REG_8BIT(0x3007), 0x00 },
 138 +       { IMX290_REG_8BIT(0x3018), 0x65 },
 139 +       { IMX290_REG_8BIT(0x3019), 0x04 },
 140 +       { IMX290_REG_8BIT(0x301a), 0x00 },
 141 +       { IMX290_REG_8BIT(0x3444), 0x20 },
 142 +       { IMX290_REG_8BIT(0x3445), 0x25 },
 143 +       { IMX290_REG_8BIT(0x303a), 0x0c },
 144 +       { IMX290_REG_8BIT(0x3040), 0x00 },
 145 +       { IMX290_REG_8BIT(0x3041), 0x00 },
 146 +       { IMX290_REG_8BIT(0x303c), 0x00 },
 147 +       { IMX290_REG_8BIT(0x303d), 0x00 },
 148 +       { IMX290_REG_8BIT(0x3042), 0x9c },
 149 +       { IMX290_REG_8BIT(0x3043), 0x07 },
 150 +       { IMX290_REG_8BIT(0x303e), 0x49 },
 151 +       { IMX290_REG_8BIT(0x303f), 0x04 },
 152 +       { IMX290_REG_8BIT(0x304b), 0x0a },
 153 +       { IMX290_REG_8BIT(0x300f), 0x00 },
 154 +       { IMX290_REG_8BIT(0x3010), 0x21 },
 155 +       { IMX290_REG_8BIT(0x3012), 0x64 },
 156 +       { IMX290_REG_8BIT(0x3016), 0x09 },
 157 +       { IMX290_REG_8BIT(0x3070), 0x02 },
 158 +       { IMX290_REG_8BIT(0x3071), 0x11 },
 159 +       { IMX290_REG_8BIT(0x309b), 0x10 },
 160 +       { IMX290_REG_8BIT(0x309c), 0x22 },
 161 +       { IMX290_REG_8BIT(0x30a2), 0x02 },
 162 +       { IMX290_REG_8BIT(0x30a6), 0x20 },
 163 +       { IMX290_REG_8BIT(0x30a8), 0x20 },
 164 +       { IMX290_REG_8BIT(0x30aa), 0x20 },
 165 +       { IMX290_REG_8BIT(0x30ac), 0x20 },
 166 +       { IMX290_REG_8BIT(0x30b0), 0x43 },
 167 +       { IMX290_REG_8BIT(0x3119), 0x9e },
 168 +       { IMX290_REG_8BIT(0x311c), 0x1e },
 169 +       { IMX290_REG_8BIT(0x311e), 0x08 },
 170 +       { IMX290_REG_8BIT(0x3128), 0x05 },
 171 +       { IMX290_REG_8BIT(0x313d), 0x83 },
 172 +       { IMX290_REG_8BIT(0x3150), 0x03 },
 173 +       { IMX290_REG_8BIT(0x317e), 0x00 },
 174 +       { IMX290_REG_8BIT(0x32b8), 0x50 },
 175 +       { IMX290_REG_8BIT(0x32b9), 0x10 },
 176 +       { IMX290_REG_8BIT(0x32ba), 0x00 },
 177 +       { IMX290_REG_8BIT(0x32bb), 0x04 },
 178 +       { IMX290_REG_8BIT(0x32c8), 0x50 },
 179 +       { IMX290_REG_8BIT(0x32c9), 0x10 },
 180 +       { IMX290_REG_8BIT(0x32ca), 0x00 },
 181 +       { IMX290_REG_8BIT(0x32cb), 0x04 },
 182 +       { IMX290_REG_8BIT(0x332c), 0xd3 },
 183 +       { IMX290_REG_8BIT(0x332d), 0x10 },
 184 +       { IMX290_REG_8BIT(0x332e), 0x0d },
 185 +       { IMX290_REG_8BIT(0x3358), 0x06 },
 186 +       { IMX290_REG_8BIT(0x3359), 0xe1 },
 187 +       { IMX290_REG_8BIT(0x335a), 0x11 },
 188 +       { IMX290_REG_8BIT(0x3360), 0x1e },
 189 +       { IMX290_REG_8BIT(0x3361), 0x61 },
 190 +       { IMX290_REG_8BIT(0x3362), 0x10 },
 191 +       { IMX290_REG_8BIT(0x33b0), 0x50 },
 192 +       { IMX290_REG_8BIT(0x33b2), 0x1a },
 193 +       { IMX290_REG_8BIT(0x33b3), 0x04 },
 194  };
 195
 196  static const struct imx290_regval imx290_1080p_settings[] = {
 197         /* mode settings */
 198 -       { 0x3007, 0x00 },
 199 -       { 0x303a, 0x0c },
 200 -       { 0x3414, 0x0a },
 201 -       { 0x3472, 0x80 },
 202 -       { 0x3473, 0x07 },
 203 -       { 0x3418, 0x38 },
 204 -       { 0x3419, 0x04 },
 205 -       { 0x3012, 0x64 },
 206 -       { 0x3013, 0x00 },
 207 -       { 0x305c, 0x18 },
 208 -       { 0x305d, 0x03 },
 209 -       { 0x305e, 0x20 },
 210 -       { 0x305f, 0x01 },
 211 -       { 0x315e, 0x1a },
 212 -       { 0x3164, 0x1a },
 213 -       { 0x3480, 0x49 },
 214 +       { IMX290_REG_8BIT(0x3007), 0x00 },
 215 +       { IMX290_REG_8BIT(0x303a), 0x0c },
 216 +       { IMX290_REG_8BIT(0x3414), 0x0a },
 217 +       { IMX290_REG_8BIT(0x3472), 0x80 },
 218 +       { IMX290_REG_8BIT(0x3473), 0x07 },
 219 +       { IMX290_REG_8BIT(0x3418), 0x38 },
 220 +       { IMX290_REG_8BIT(0x3419), 0x04 },
 221 +       { IMX290_REG_8BIT(0x3012), 0x64 },
 222 +       { IMX290_REG_8BIT(0x3013), 0x00 },
 223 +       { IMX290_REG_8BIT(0x305c), 0x18 },
 224 +       { IMX290_REG_8BIT(0x305d), 0x03 },
 225 +       { IMX290_REG_8BIT(0x305e), 0x20 },
 226 +       { IMX290_REG_8BIT(0x305f), 0x01 },
 227 +       { IMX290_REG_8BIT(0x315e), 0x1a },
 228 +       { IMX290_REG_8BIT(0x3164), 0x1a },
 229 +       { IMX290_REG_8BIT(0x3480), 0x49 },
 230         /* data rate settings */
 231 -       { 0x3405, 0x10 },
 232 -       { 0x3446, 0x57 },
 233 -       { 0x3447, 0x00 },
 234 -       { 0x3448, 0x37 },
 235 -       { 0x3449, 0x00 },
 236 -       { 0x344a, 0x1f },
 237 -       { 0x344b, 0x00 },
 238 -       { 0x344c, 0x1f },
 239 -       { 0x344d, 0x00 },
 240 -       { 0x344e, 0x1f },
 241 -       { 0x344f, 0x00 },
 242 -       { 0x3450, 0x77 },
 243 -       { 0x3451, 0x00 },
 244 -       { 0x3452, 0x1f },
 245 -       { 0x3453, 0x00 },
 246 -       { 0x3454, 0x17 },
 247 -       { 0x3455, 0x00 },
 248 +       { IMX290_REG_8BIT(0x3405), 0x10 },
 249 +       { IMX290_REG_8BIT(0x3446), 0x57 },
 250 +       { IMX290_REG_8BIT(0x3447), 0x00 },
 251 +       { IMX290_REG_8BIT(0x3448), 0x37 },
 252 +       { IMX290_REG_8BIT(0x3449), 0x00 },
 253 +       { IMX290_REG_8BIT(0x344a), 0x1f },
 254 +       { IMX290_REG_8BIT(0x344b), 0x00 },
 255 +       { IMX290_REG_8BIT(0x344c), 0x1f },
 256 +       { IMX290_REG_8BIT(0x344d), 0x00 },
 257 +       { IMX290_REG_8BIT(0x344e), 0x1f },
 258 +       { IMX290_REG_8BIT(0x344f), 0x00 },
 259 +       { IMX290_REG_8BIT(0x3450), 0x77 },
 260 +       { IMX290_REG_8BIT(0x3451), 0x00 },
 261 +       { IMX290_REG_8BIT(0x3452), 0x1f },
 262 +       { IMX290_REG_8BIT(0x3453), 0x00 },
 263 +       { IMX290_REG_8BIT(0x3454), 0x17 },
 264 +       { IMX290_REG_8BIT(0x3455), 0x00 },
 265  };
 266
 267  static const struct imx290_regval imx290_720p_settings[] = {
 268         /* mode settings */
 269 -       { 0x3007, 0x10 },
 270 -       { 0x303a, 0x06 },
 271 -       { 0x3414, 0x04 },
 272 -       { 0x3472, 0x00 },
 273 -       { 0x3473, 0x05 },
 274 -       { 0x3418, 0xd0 },
 275 -       { 0x3419, 0x02 },
 276 -       { 0x3012, 0x64 },
 277 -       { 0x3013, 0x00 },
 278 -       { 0x305c, 0x20 },
 279 -       { 0x305d, 0x00 },
 280 -       { 0x305e, 0x20 },
 281 -       { 0x305f, 0x01 },
 282 -       { 0x315e, 0x1a },
 283 -       { 0x3164, 0x1a },
 284 -       { 0x3480, 0x49 },
 285 +       { IMX290_REG_8BIT(0x3007), 0x10 },
 286 +       { IMX290_REG_8BIT(0x303a), 0x06 },
 287 +       { IMX290_REG_8BIT(0x3414), 0x04 },
 288 +       { IMX290_REG_8BIT(0x3472), 0x00 },
 289 +       { IMX290_REG_8BIT(0x3473), 0x05 },
 290 +       { IMX290_REG_8BIT(0x3418), 0xd0 },
 291 +       { IMX290_REG_8BIT(0x3419), 0x02 },
 292 +       { IMX290_REG_8BIT(0x3012), 0x64 },
 293 +       { IMX290_REG_8BIT(0x3013), 0x00 },
 294 +       { IMX290_REG_8BIT(0x305c), 0x20 },
 295 +       { IMX290_REG_8BIT(0x305d), 0x00 },
 296 +       { IMX290_REG_8BIT(0x305e), 0x20 },
 297 +       { IMX290_REG_8BIT(0x305f), 0x01 },
 298 +       { IMX290_REG_8BIT(0x315e), 0x1a },
 299 +       { IMX290_REG_8BIT(0x3164), 0x1a },
 300 +       { IMX290_REG_8BIT(0x3480), 0x49 },
 301         /* data rate settings */
 302 -       { 0x3405, 0x10 },
 303 -       { 0x3446, 0x4f },
 304 -       { 0x3447, 0x00 },
 305 -       { 0x3448, 0x2f },
 306 -       { 0x3449, 0x00 },
 307 -       { 0x344a, 0x17 },
 308 -       { 0x344b, 0x00 },
 309 -       { 0x344c, 0x17 },
 310 -       { 0x344d, 0x00 },
 311 -       { 0x344e, 0x17 },
 312 -       { 0x344f, 0x00 },
 313 -       { 0x3450, 0x57 },
 314 -       { 0x3451, 0x00 },
 315 -       { 0x3452, 0x17 },
 316 -       { 0x3453, 0x00 },
 317 -       { 0x3454, 0x17 },
 318 -       { 0x3455, 0x00 },
 319 +       { IMX290_REG_8BIT(0x3405), 0x10 },
 320 +       { IMX290_REG_8BIT(0x3446), 0x4f },
 321 +       { IMX290_REG_8BIT(0x3447), 0x00 },
 322 +       { IMX290_REG_8BIT(0x3448), 0x2f },
 323 +       { IMX290_REG_8BIT(0x3449), 0x00 },
 324 +       { IMX290_REG_8BIT(0x344a), 0x17 },
 325 +       { IMX290_REG_8BIT(0x344b), 0x00 },
 326 +       { IMX290_REG_8BIT(0x344c), 0x17 },
 327 +       { IMX290_REG_8BIT(0x344d), 0x00 },
 328 +       { IMX290_REG_8BIT(0x344e), 0x17 },
 329 +       { IMX290_REG_8BIT(0x344f), 0x00 },
 330 +       { IMX290_REG_8BIT(0x3450), 0x57 },
 331 +       { IMX290_REG_8BIT(0x3451), 0x00 },
 332 +       { IMX290_REG_8BIT(0x3452), 0x17 },
 333 +       { IMX290_REG_8BIT(0x3453), 0x00 },
 334 +       { IMX290_REG_8BIT(0x3454), 0x17 },
 335 +       { IMX290_REG_8BIT(0x3455), 0x00 },
 336  };
 337
 338  static const struct imx290_regval imx290_10bit_settings[] = {
 339 -       { 0x3005, 0x00},
 340 -       { 0x3046, 0x00},
 341 -       { 0x3129, 0x1d},
 342 -       { 0x317c, 0x12},
 343 -       { 0x31ec, 0x37},
 344 -       { 0x3441, 0x0a},
 345 -       { 0x3442, 0x0a},
 346 -       { 0x300a, 0x3c},
 347 -       { 0x300b, 0x00},
 348 +       { IMX290_REG_8BIT(0x3005), 0x00},
 349 +       { IMX290_REG_8BIT(0x3046), 0x00},
 350 +       { IMX290_REG_8BIT(0x3129), 0x1d},
 351 +       { IMX290_REG_8BIT(0x317c), 0x12},
 352 +       { IMX290_REG_8BIT(0x31ec), 0x37},
 353 +       { IMX290_REG_8BIT(0x3441), 0x0a},
 354 +       { IMX290_REG_8BIT(0x3442), 0x0a},
 355 +       { IMX290_REG_8BIT(0x300a), 0x3c},
 356 +       { IMX290_REG_8BIT(0x300b), 0x00},
 357  };
 358
 359  static const struct imx290_regval imx290_12bit_settings[] = {
 360 -       { 0x3005, 0x01 },
 361 -       { 0x3046, 0x01 },
 362 -       { 0x3129, 0x00 },
 363 -       { 0x317c, 0x00 },
 364 -       { 0x31ec, 0x0e },
 365 -       { 0x3441, 0x0c },
 366 -       { 0x3442, 0x0c },
 367 -       { 0x300a, 0xf0 },
 368 -       { 0x300b, 0x00 },
 369 +       { IMX290_REG_8BIT(0x3005), 0x01 },
 370 +       { IMX290_REG_8BIT(0x3046), 0x01 },
 371 +       { IMX290_REG_8BIT(0x3129), 0x00 },
 372 +       { IMX290_REG_8BIT(0x317c), 0x00 },
 373 +       { IMX290_REG_8BIT(0x31ec), 0x0e },
 374 +       { IMX290_REG_8BIT(0x3441), 0x0c },
 375 +       { IMX290_REG_8BIT(0x3442), 0x0c },
 376 +       { IMX290_REG_8BIT(0x300a), 0xf0 },
 377 +       { IMX290_REG_8BIT(0x300b), 0x00 },
 378  };
 379
 380  /* supported link frequencies */
 381 @@ -362,33 +368,35 @@ static inline struct imx290 *to_imx290(s
 382         return container_of(_sd, struct imx290, sd);
 383  }
 384
 385 -static inline int __always_unused imx290_read_reg(struct imx290 *imx290, u16 addr, u8 *value)
 386 +static int __always_unused imx290_read_reg(struct imx290 *imx290, u32 addr, u32 *value)
 387  {
 388 -       unsigned int regval;
 389 +       u8 data[3] = { 0, 0, 0 };
 390         int ret;
 391
 392 -       ret = regmap_read(imx290->regmap, addr, &regval);
 393 -       if (ret) {
 394 -               dev_err(imx290->dev, "Failed to read register 0x%04x: %d\n",
 395 -                       addr, ret);
 396 +       ret = regmap_raw_read(imx290->regmap, addr & IMX290_REG_ADDR_MASK,
 397 +                             data, (addr >> IMX290_REG_SIZE_SHIFT) & 3);
 398 +       if (ret < 0) {
 399 +               dev_err(imx290->dev, "%u-bit read from 0x%04x failed: %d\n",
 400 +                        ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8,
 401 +                        addr & IMX290_REG_ADDR_MASK, ret);
 402                 return ret;
 403         }
 404
 405 -       *value = regval & 0xff;
 406 -
 407 +       *value = (data[2] << 16) | (data[1] << 8) | data[0];
 408         return 0;
 409  }
 410
 411 -static int imx290_write_reg(struct imx290 *imx290, u16 addr, u8 value)
 412 +static int imx290_write_reg(struct imx290 *imx290, u32 addr, u32 value)
 413  {
 414 +       u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 };
 415         int ret;
 416
 417 -       ret = regmap_write(imx290->regmap, addr, value);
 418 -       if (ret) {
 419 -               dev_err(imx290->dev, "Failed to write register 0x%04x: %d\n",
 420 -                       addr, ret);
 421 -               return ret;
 422 -       }
 423 +       ret = regmap_raw_write(imx290->regmap, addr & IMX290_REG_ADDR_MASK,
 424 +                              data, (addr >> IMX290_REG_SIZE_SHIFT) & 3);
 425 +       if (ret < 0)
 426 +               dev_err(imx290->dev, "%u-bit write to 0x%04x failed: %d\n",
 427 +                        ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8,
 428 +                        addr & IMX290_REG_ADDR_MASK, ret);
 429
 430         return ret;
 431  }