target/linux/bcm27xx/patches-5.4/950-0792-media-irs1125-Atomic-access-to-imager-reconfiguratio.patch

   1 From 3afb0a757409f5186812b3ea36c61a03855e47d2 Mon Sep 17 00:00:00 2001
   2 From: Markus Proeller <markus.proeller@pieye.org>
   3 Date: Tue, 16 Jun 2020 13:31:36 +0200
   4 Subject: [PATCH] media: irs1125: Atomic access to imager
   5  reconfiguration
   6
   7 Instead of changing the exposure and framerate settings for all sequences,
   8 they can be changed for every sequence individually now. Therefore the
   9 IRS1125_CID_SAFE_RECONFIG ctrl has been removed and replaced by
  10 IRS1125_CID_SAFE_RECONFIG_S<seq_num>_EXPO and *_FRAME ctrls.
  11
  12 The consistency check in the sequence ctrl IRS1125_CID_SEQ_CONFIG
  13 is removed.
  14
  15 Signed-off-by: Markus Proeller <markus.proeller@pieye.org>
  16 ---
  17  drivers/media/i2c/irs1125.c | 224 ++++++++++++++++++++++++------------
  18  drivers/media/i2c/irs1125.h |  68 ++++++++---
  19  2 files changed, 204 insertions(+), 88 deletions(-)
  20
  21 --- a/drivers/media/i2c/irs1125.c
  22 +++ b/drivers/media/i2c/irs1125.c
  23 @@ -89,6 +89,52 @@ static inline struct irs1125 *to_state(s
  24         return container_of(sd, struct irs1125, sd);
  25  }
  26
  27 +static const char *expo_ctrl_names[IRS1125_NUM_SEQ_ENTRIES] = {
  28 +       "safe reconfiguration of exposure of sequence 0",
  29 +       "safe reconfiguration of exposure of sequence 1",
  30 +       "safe reconfiguration of exposure of sequence 2",
  31 +       "safe reconfiguration of exposure of sequence 3",
  32 +       "safe reconfiguration of exposure of sequence 4",
  33 +       "safe reconfiguration of exposure of sequence 5",
  34 +       "safe reconfiguration of exposure of sequence 6",
  35 +       "safe reconfiguration of exposure of sequence 7",
  36 +       "safe reconfiguration of exposure of sequence 8",
  37 +       "safe reconfiguration of exposure of sequence 9",
  38 +       "safe reconfiguration of exposure of sequence 10",
  39 +       "safe reconfiguration of exposure of sequence 11",
  40 +       "safe reconfiguration of exposure of sequence 12",
  41 +       "safe reconfiguration of exposure of sequence 13",
  42 +       "safe reconfiguration of exposure of sequence 14",
  43 +       "safe reconfiguration of exposure of sequence 15",
  44 +       "safe reconfiguration of exposure of sequence 16",
  45 +       "safe reconfiguration of exposure of sequence 17",
  46 +       "safe reconfiguration of exposure of sequence 18",
  47 +       "safe reconfiguration of exposure of sequence 19",
  48 +};
  49 +
  50 +static const char *frame_ctrl_names[IRS1125_NUM_SEQ_ENTRIES] = {
  51 +       "safe reconfiguration of framerate of sequence 0",
  52 +       "safe reconfiguration of framerate of sequence 1",
  53 +       "safe reconfiguration of framerate of sequence 2",
  54 +       "safe reconfiguration of framerate of sequence 3",
  55 +       "safe reconfiguration of framerate of sequence 4",
  56 +       "safe reconfiguration of framerate of sequence 5",
  57 +       "safe reconfiguration of framerate of sequence 6",
  58 +       "safe reconfiguration of framerate of sequence 7",
  59 +       "safe reconfiguration of framerate of sequence 8",
  60 +       "safe reconfiguration of framerate of sequence 9",
  61 +       "safe reconfiguration of framerate of sequence 10",
  62 +       "safe reconfiguration of framerate of sequence 11",
  63 +       "safe reconfiguration of framerate of sequence 12",
  64 +       "safe reconfiguration of framerate of sequence 13",
  65 +       "safe reconfiguration of framerate of sequence 14",
  66 +       "safe reconfiguration of framerate of sequence 15",
  67 +       "safe reconfiguration of framerate of sequence 16",
  68 +       "safe reconfiguration of framerate of sequence 17",
  69 +       "safe reconfiguration of framerate of sequence 18",
  70 +       "safe reconfiguration of framerate of sequence 19",
  71 +};
  72 +
  73  static struct regval_list irs1125_26mhz[] = {
  74         {0xB017, 0x0413},
  75         {0xB086, 0x3535},
  76 @@ -561,36 +607,57 @@ static int irs1125_s_ctrl(struct v4l2_ct
  77         struct irs1125 *dev = container_of(ctrl->handler,
  78                                         struct irs1125, ctrl_handler);
  79         struct i2c_client *client = v4l2_get_subdevdata(&dev->sd);
  80 -       int err, i;
  81         struct irs1125_mod_pll *mod_cur, *mod_new;
  82 -       struct irs1125_seq_cfg *cfg_cur, *cfg_new;
  83         u16 addr, val;
  84 -
  85 -       err = 0;
  86 +       int err = 0, i;
  87
  88         switch (ctrl->id) {
  89 -       case IRS1125_CID_SAFE_RECONFIG:
  90 -       {
  91 -               struct irs1125_illu *illu_cur, *illu_new;
  92 -
  93 -               illu_new = (struct irs1125_illu *)ctrl->p_new.p;
  94 -               illu_cur = (struct irs1125_illu *)ctrl->p_cur.p;
  95 -               for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {
  96 -                       if (illu_cur[i].exposure != illu_new[i].exposure) {
  97 -                               addr = 0xA850 + i * 2;
  98 -                               val = illu_new[i].exposure;
  99 -                               err = irs1125_write(&dev->sd, addr, val);
 100 -                               if (err < 0)
 101 -                                       break;
 102 -                       }
 103 -                       if (illu_cur[i].framerate != illu_new[i].framerate) {
 104 -                               addr = 0xA851 + i * 2;
 105 -                               val = illu_new[i].framerate;
 106 -                               err = irs1125_write(&dev->sd, addr, val);
 107 -                               if (err < 0)
 108 -                                       break;
 109 -                       }
 110 -               }
 111 +       case IRS1125_CID_SAFE_RECONFIG_S0_EXPO:
 112 +       case IRS1125_CID_SAFE_RECONFIG_S0_FRAME:
 113 +       case IRS1125_CID_SAFE_RECONFIG_S1_EXPO:
 114 +       case IRS1125_CID_SAFE_RECONFIG_S1_FRAME:
 115 +       case IRS1125_CID_SAFE_RECONFIG_S2_EXPO:
 116 +       case IRS1125_CID_SAFE_RECONFIG_S2_FRAME:
 117 +       case IRS1125_CID_SAFE_RECONFIG_S3_EXPO:
 118 +       case IRS1125_CID_SAFE_RECONFIG_S3_FRAME:
 119 +       case IRS1125_CID_SAFE_RECONFIG_S4_EXPO:
 120 +       case IRS1125_CID_SAFE_RECONFIG_S4_FRAME:
 121 +       case IRS1125_CID_SAFE_RECONFIG_S5_EXPO:
 122 +       case IRS1125_CID_SAFE_RECONFIG_S5_FRAME:
 123 +       case IRS1125_CID_SAFE_RECONFIG_S6_EXPO:
 124 +       case IRS1125_CID_SAFE_RECONFIG_S6_FRAME:
 125 +       case IRS1125_CID_SAFE_RECONFIG_S7_EXPO:
 126 +       case IRS1125_CID_SAFE_RECONFIG_S7_FRAME:
 127 +       case IRS1125_CID_SAFE_RECONFIG_S8_EXPO:
 128 +       case IRS1125_CID_SAFE_RECONFIG_S8_FRAME:
 129 +       case IRS1125_CID_SAFE_RECONFIG_S9_EXPO:
 130 +       case IRS1125_CID_SAFE_RECONFIG_S9_FRAME:
 131 +       case IRS1125_CID_SAFE_RECONFIG_S10_EXPO:
 132 +       case IRS1125_CID_SAFE_RECONFIG_S10_FRAME:
 133 +       case IRS1125_CID_SAFE_RECONFIG_S11_EXPO:
 134 +       case IRS1125_CID_SAFE_RECONFIG_S11_FRAME:
 135 +       case IRS1125_CID_SAFE_RECONFIG_S12_EXPO:
 136 +       case IRS1125_CID_SAFE_RECONFIG_S12_FRAME:
 137 +       case IRS1125_CID_SAFE_RECONFIG_S13_EXPO:
 138 +       case IRS1125_CID_SAFE_RECONFIG_S13_FRAME:
 139 +       case IRS1125_CID_SAFE_RECONFIG_S14_EXPO:
 140 +       case IRS1125_CID_SAFE_RECONFIG_S14_FRAME:
 141 +       case IRS1125_CID_SAFE_RECONFIG_S15_EXPO:
 142 +       case IRS1125_CID_SAFE_RECONFIG_S15_FRAME:
 143 +       case IRS1125_CID_SAFE_RECONFIG_S16_EXPO:
 144 +       case IRS1125_CID_SAFE_RECONFIG_S16_FRAME:
 145 +       case IRS1125_CID_SAFE_RECONFIG_S17_EXPO:
 146 +       case IRS1125_CID_SAFE_RECONFIG_S17_FRAME:
 147 +       case IRS1125_CID_SAFE_RECONFIG_S18_EXPO:
 148 +       case IRS1125_CID_SAFE_RECONFIG_S18_FRAME:
 149 +       case IRS1125_CID_SAFE_RECONFIG_S19_EXPO:
 150 +       case IRS1125_CID_SAFE_RECONFIG_S19_FRAME: {
 151 +               unsigned int offset = ctrl->id -
 152 +                       IRS1125_CID_SAFE_RECONFIG_S0_EXPO;
 153 +
 154 +               err = irs1125_write(&dev->sd,
 155 +                                   IRS1125_REG_SAFE_RECONFIG + offset,
 156 +                                   ctrl->val);
 157                 break;
 158         }
 159         case IRS1125_CID_MOD_PLL:
 160 @@ -655,40 +722,40 @@ static int irs1125_s_ctrl(struct v4l2_ct
 161                         }
 162                 }
 163                 break;
 164 -       case IRS1125_CID_SEQ_CONFIG:
 165 +       case IRS1125_CID_SEQ_CONFIG: {
 166 +               struct irs1125_seq_cfg *cfg_new;
 167 +
 168                 cfg_new = (struct irs1125_seq_cfg *)ctrl->p_new.p;
 169 -               cfg_cur = (struct irs1125_seq_cfg *)ctrl->p_cur.p;
 170                 for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {
 171 -                       if (cfg_cur[i].exposure != cfg_new[i].exposure) {
 172 -                               addr = IRS1125_REG_DMEM_SHADOW + i * 4;
 173 -                               val = cfg_new[i].exposure;
 174 -                               err = irs1125_write(&dev->sd, addr, val);
 175 -                               if (err < 0)
 176 -                                       break;
 177 -                       }
 178 -                       if (cfg_cur[i].framerate != cfg_new[i].framerate) {
 179 -                               addr = IRS1125_REG_DMEM_SHADOW + 1 + i * 4;
 180 -                               val = cfg_new[i].framerate;
 181 -                               err = irs1125_write(&dev->sd, addr, val);
 182 -                               if (err < 0)
 183 -                                       break;
 184 -                       }
 185 -                       if (cfg_cur[i].ps != cfg_new[i].ps) {
 186 -                               addr = IRS1125_REG_DMEM_SHADOW + 2 + i * 4;
 187 -                               val = cfg_new[i].ps;
 188 -                               err = irs1125_write(&dev->sd, addr, val);
 189 -                               if (err < 0)
 190 -                                       break;
 191 -                       }
 192 -                       if (cfg_cur[i].pll != cfg_new[i].pll) {
 193 -                               addr = IRS1125_REG_DMEM_SHADOW + 3 + i * 4;
 194 -                               val = cfg_new[i].pll;
 195 -                               err = irs1125_write(&dev->sd, addr, val);
 196 -                               if (err < 0)
 197 -                                       break;
 198 -                       }
 199 +                       unsigned int seq_offset = i * 4;
 200 +                       u16 addr, val;
 201 +
 202 +                       addr = IRS1125_REG_DMEM_SHADOW + seq_offset;
 203 +                       val = cfg_new[i].exposure;
 204 +                       err = irs1125_write(&dev->sd, addr, val);
 205 +                       if (err < 0)
 206 +                               break;
 207 +
 208 +                       addr = IRS1125_REG_DMEM_SHADOW + 1 + seq_offset;
 209 +                       val = cfg_new[i].framerate;
 210 +                       err = irs1125_write(&dev->sd, addr, val);
 211 +                       if (err < 0)
 212 +                               break;
 213 +
 214 +                       addr = IRS1125_REG_DMEM_SHADOW + 2 + seq_offset;
 215 +                       val = cfg_new[i].ps;
 216 +                       err = irs1125_write(&dev->sd, addr, val);
 217 +                       if (err < 0)
 218 +                               break;
 219 +
 220 +                       addr = IRS1125_REG_DMEM_SHADOW + 3 + seq_offset;
 221 +                       val = cfg_new[i].pll;
 222 +                       err = irs1125_write(&dev->sd, addr, val);
 223 +                       if (err < 0)
 224 +                               break;
 225                 }
 226                 break;
 227 +       }
 228         case IRS1125_CID_NUM_SEQS:
 229                 err = irs1125_write(&dev->sd, 0xA88D, ctrl->val - 1);
 230                 if (err >= 0)
 231 @@ -760,19 +827,6 @@ static const struct v4l2_ctrl_config irs
 232                         IRS1125_NUM_MOD_PLLS}
 233         }, {
 234                 .ops = &irs1125_ctrl_ops,
 235 -               .id = IRS1125_CID_SAFE_RECONFIG,
 236 -               .name = "Change exposure and pause of single seq",
 237 -               .type = V4L2_CTRL_TYPE_U16,
 238 -               .flags = V4L2_CTRL_FLAG_HAS_PAYLOAD,
 239 -               .min = 0,
 240 -               .max = U16_MAX,
 241 -               .step = 1,
 242 -               .def = 0,
 243 -               .elem_size = sizeof(u16),
 244 -               .dims = {sizeof(struct irs1125_illu) / sizeof(u16),
 245 -                       IRS1125_NUM_SEQ_ENTRIES}
 246 -       }, {
 247 -               .ops = &irs1125_ctrl_ops,
 248                 .id = IRS1125_CID_SEQ_CONFIG,
 249                 .name = "Change sequence settings",
 250                 .type = V4L2_CTRL_TYPE_U16,
 251 @@ -900,9 +954,16 @@ static int irs1125_ctrls_init(struct irs
 252  {
 253         struct v4l2_ctrl *ctrl;
 254         int err, i;
 255 -       struct v4l2_ctrl_handler *hdl;
 256 +       struct v4l2_ctrl_handler *hdl = &sensor->ctrl_handler;
 257 +       struct v4l2_ctrl_config ctrl_cfg = {
 258 +               .ops = &irs1125_ctrl_ops,
 259 +               .type = V4L2_CTRL_TYPE_INTEGER,
 260 +               .min = 0,
 261 +               .max = U16_MAX,
 262 +               .step = 1,
 263 +               .def = 0x1000
 264 +       };
 265
 266 -       hdl = &sensor->ctrl_handler;
 267         v4l2_ctrl_handler_init(hdl, ARRAY_SIZE(irs1125_custom_ctrls));
 268
 269         for (i = 0; i < ARRAY_SIZE(irs1125_custom_ctrls); i++)  {
 270 @@ -923,6 +984,27 @@ static int irs1125_ctrls_init(struct irs
 271                 goto error_ctrls;
 272         }
 273
 274 +       for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {
 275 +               ctrl_cfg.name = expo_ctrl_names[i];
 276 +               ctrl_cfg.id = IRS1125_CID_SAFE_RECONFIG_S0_EXPO + i * 2;
 277 +               ctrl = v4l2_ctrl_new_custom(hdl, &ctrl_cfg,
 278 +                                           NULL);
 279 +               if (!ctrl)
 280 +                       dev_err(dev, "Failed to init exposure control %s\n",
 281 +                               ctrl_cfg.name);
 282 +       }
 283 +
 284 +       ctrl_cfg.def = 0;
 285 +       for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {
 286 +               ctrl_cfg.name = frame_ctrl_names[i];
 287 +               ctrl_cfg.id = IRS1125_CID_SAFE_RECONFIG_S0_FRAME + i * 2;
 288 +               ctrl = v4l2_ctrl_new_custom(hdl, &ctrl_cfg,
 289 +                                           NULL);
 290 +               if (!ctrl)
 291 +                       dev_err(dev, "Failed to init framerate control %s\n",
 292 +                               ctrl_cfg.name);
 293 +       }
 294 +
 295         sensor->sd.ctrl_handler = hdl;
 296         return 0;
 297
 298 --- a/drivers/media/i2c/irs1125.h
 299 +++ b/drivers/media/i2c/irs1125.h
 300 @@ -21,18 +21,57 @@
 301  #define IRS1125_NUM_SEQ_ENTRIES 20
 302  #define IRS1125_NUM_MOD_PLLS 4
 303
 304 -#define IRS1125_CID_CUSTOM_BASE        (V4L2_CID_USER_BASE | 0xf000)
 305 -#define IRS1125_CID_SAFE_RECONFIG      (IRS1125_CID_CUSTOM_BASE + 0)
 306 -#define IRS1125_CID_CONTINUOUS_TRIG    (IRS1125_CID_CUSTOM_BASE + 1)
 307 -#define IRS1125_CID_TRIGGER            (IRS1125_CID_CUSTOM_BASE + 2)
 308 -#define IRS1125_CID_RECONFIG           (IRS1125_CID_CUSTOM_BASE + 3)
 309 -#define IRS1125_CID_ILLU_ON            (IRS1125_CID_CUSTOM_BASE + 4)
 310 -#define IRS1125_CID_NUM_SEQS           (IRS1125_CID_CUSTOM_BASE + 5)
 311 -#define IRS1125_CID_MOD_PLL            (IRS1125_CID_CUSTOM_BASE + 6)
 312 -#define IRS1125_CID_SEQ_CONFIG         (IRS1125_CID_CUSTOM_BASE + 7)
 313 -#define IRS1125_CID_IDENT0             (IRS1125_CID_CUSTOM_BASE + 8)
 314 -#define IRS1125_CID_IDENT1             (IRS1125_CID_CUSTOM_BASE + 9)
 315 -#define IRS1125_CID_IDENT2             (IRS1125_CID_CUSTOM_BASE + 10)
 316 +#define IRS1125_CID_CUSTOM_BASE                        (V4L2_CID_USER_BASE | 0xf000)
 317 +#define IRS1125_CID_CONTINUOUS_TRIG            (IRS1125_CID_CUSTOM_BASE + 1)
 318 +#define IRS1125_CID_TRIGGER                    (IRS1125_CID_CUSTOM_BASE + 2)
 319 +#define IRS1125_CID_RECONFIG                   (IRS1125_CID_CUSTOM_BASE + 3)
 320 +#define IRS1125_CID_ILLU_ON                    (IRS1125_CID_CUSTOM_BASE + 4)
 321 +#define IRS1125_CID_NUM_SEQS                   (IRS1125_CID_CUSTOM_BASE + 5)
 322 +#define IRS1125_CID_MOD_PLL                    (IRS1125_CID_CUSTOM_BASE + 6)
 323 +#define IRS1125_CID_SEQ_CONFIG                 (IRS1125_CID_CUSTOM_BASE + 7)
 324 +#define IRS1125_CID_IDENT0                     (IRS1125_CID_CUSTOM_BASE + 8)
 325 +#define IRS1125_CID_IDENT1                     (IRS1125_CID_CUSTOM_BASE + 9)
 326 +#define IRS1125_CID_IDENT2                     (IRS1125_CID_CUSTOM_BASE + 10)
 327 +#define IRS1125_CID_SAFE_RECONFIG_S0_EXPO      (IRS1125_CID_CUSTOM_BASE + 11)
 328 +#define IRS1125_CID_SAFE_RECONFIG_S0_FRAME     (IRS1125_CID_CUSTOM_BASE + 12)
 329 +#define IRS1125_CID_SAFE_RECONFIG_S1_EXPO      (IRS1125_CID_CUSTOM_BASE + 13)
 330 +#define IRS1125_CID_SAFE_RECONFIG_S1_FRAME     (IRS1125_CID_CUSTOM_BASE + 14)
 331 +#define IRS1125_CID_SAFE_RECONFIG_S2_EXPO      (IRS1125_CID_CUSTOM_BASE + 15)
 332 +#define IRS1125_CID_SAFE_RECONFIG_S2_FRAME     (IRS1125_CID_CUSTOM_BASE + 16)
 333 +#define IRS1125_CID_SAFE_RECONFIG_S3_EXPO      (IRS1125_CID_CUSTOM_BASE + 17)
 334 +#define IRS1125_CID_SAFE_RECONFIG_S3_FRAME     (IRS1125_CID_CUSTOM_BASE + 18)
 335 +#define IRS1125_CID_SAFE_RECONFIG_S4_EXPO      (IRS1125_CID_CUSTOM_BASE + 19)
 336 +#define IRS1125_CID_SAFE_RECONFIG_S4_FRAME     (IRS1125_CID_CUSTOM_BASE + 20)
 337 +#define IRS1125_CID_SAFE_RECONFIG_S5_EXPO      (IRS1125_CID_CUSTOM_BASE + 21)
 338 +#define IRS1125_CID_SAFE_RECONFIG_S5_FRAME     (IRS1125_CID_CUSTOM_BASE + 22)
 339 +#define IRS1125_CID_SAFE_RECONFIG_S6_EXPO      (IRS1125_CID_CUSTOM_BASE + 23)
 340 +#define IRS1125_CID_SAFE_RECONFIG_S6_FRAME     (IRS1125_CID_CUSTOM_BASE + 24)
 341 +#define IRS1125_CID_SAFE_RECONFIG_S7_EXPO      (IRS1125_CID_CUSTOM_BASE + 25)
 342 +#define IRS1125_CID_SAFE_RECONFIG_S7_FRAME     (IRS1125_CID_CUSTOM_BASE + 26)
 343 +#define IRS1125_CID_SAFE_RECONFIG_S8_EXPO      (IRS1125_CID_CUSTOM_BASE + 27)
 344 +#define IRS1125_CID_SAFE_RECONFIG_S8_FRAME     (IRS1125_CID_CUSTOM_BASE + 28)
 345 +#define IRS1125_CID_SAFE_RECONFIG_S9_EXPO      (IRS1125_CID_CUSTOM_BASE + 29)
 346 +#define IRS1125_CID_SAFE_RECONFIG_S9_FRAME     (IRS1125_CID_CUSTOM_BASE + 30)
 347 +#define IRS1125_CID_SAFE_RECONFIG_S10_EXPO     (IRS1125_CID_CUSTOM_BASE + 31)
 348 +#define IRS1125_CID_SAFE_RECONFIG_S10_FRAME    (IRS1125_CID_CUSTOM_BASE + 32)
 349 +#define IRS1125_CID_SAFE_RECONFIG_S11_EXPO     (IRS1125_CID_CUSTOM_BASE + 33)
 350 +#define IRS1125_CID_SAFE_RECONFIG_S11_FRAME    (IRS1125_CID_CUSTOM_BASE + 34)
 351 +#define IRS1125_CID_SAFE_RECONFIG_S12_EXPO     (IRS1125_CID_CUSTOM_BASE + 35)
 352 +#define IRS1125_CID_SAFE_RECONFIG_S12_FRAME    (IRS1125_CID_CUSTOM_BASE + 36)
 353 +#define IRS1125_CID_SAFE_RECONFIG_S13_EXPO     (IRS1125_CID_CUSTOM_BASE + 37)
 354 +#define IRS1125_CID_SAFE_RECONFIG_S13_FRAME    (IRS1125_CID_CUSTOM_BASE + 38)
 355 +#define IRS1125_CID_SAFE_RECONFIG_S14_EXPO     (IRS1125_CID_CUSTOM_BASE + 39)
 356 +#define IRS1125_CID_SAFE_RECONFIG_S14_FRAME    (IRS1125_CID_CUSTOM_BASE + 40)
 357 +#define IRS1125_CID_SAFE_RECONFIG_S15_EXPO     (IRS1125_CID_CUSTOM_BASE + 41)
 358 +#define IRS1125_CID_SAFE_RECONFIG_S15_FRAME    (IRS1125_CID_CUSTOM_BASE + 42)
 359 +#define IRS1125_CID_SAFE_RECONFIG_S16_EXPO     (IRS1125_CID_CUSTOM_BASE + 43)
 360 +#define IRS1125_CID_SAFE_RECONFIG_S16_FRAME    (IRS1125_CID_CUSTOM_BASE + 44)
 361 +#define IRS1125_CID_SAFE_RECONFIG_S17_EXPO     (IRS1125_CID_CUSTOM_BASE + 45)
 362 +#define IRS1125_CID_SAFE_RECONFIG_S17_FRAME    (IRS1125_CID_CUSTOM_BASE + 46)
 363 +#define IRS1125_CID_SAFE_RECONFIG_S18_EXPO     (IRS1125_CID_CUSTOM_BASE + 47)
 364 +#define IRS1125_CID_SAFE_RECONFIG_S18_FRAME    (IRS1125_CID_CUSTOM_BASE + 48)
 365 +#define IRS1125_CID_SAFE_RECONFIG_S19_EXPO     (IRS1125_CID_CUSTOM_BASE + 49)
 366 +#define IRS1125_CID_SAFE_RECONFIG_S19_FRAME    (IRS1125_CID_CUSTOM_BASE + 50)
 367
 368  struct irs1125_seq_cfg {
 369         __u16 exposure;
 370 @@ -41,11 +80,6 @@ struct irs1125_seq_cfg {
 371         __u16 pll;
 372  };
 373
 374 -struct irs1125_illu {
 375 -       __u16 exposure;
 376 -       __u16 framerate;
 377 -};
 378 -
 379  struct irs1125_mod_pll {
 380         __u16 pllcfg1;
 381         __u16 pllcfg2;