target/linux/bcm27xx/patches-5.4/950-0786-PCI-brcmstb-Add-DT-property-to-control-L1SS.patch

   1 From faca7230ba711f7f966cd51bf46f83c5848a8623 Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.com>
   3 Date: Thu, 11 Jun 2020 09:57:03 +0100
   4 Subject: [PATCH] PCI: brcmstb: Add DT property to control L1SS
   5
   6 The BRCM PCIe block has controls to enable control of the CLKREQ#
   7 signal by the L1SS, and to gate the refclk with the CLKREQ# input.
   8 These controls are mutually exclusive - the upstream code sets the
   9 latter, but some use cases require the former.
  10
  11 Add a Device Tree property - brcm,enable-l1ss - to switch to the
  12 L1SS configuration.
  13
  14 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  15 ---
  16  drivers/pci/controller/pcie-brcmstb.c | 30 ++++++++++++++++++++-------
  17  1 file changed, 23 insertions(+), 7 deletions(-)
  18
  19 --- a/drivers/pci/controller/pcie-brcmstb.c
  20 +++ b/drivers/pci/controller/pcie-brcmstb.c
  21 @@ -102,8 +102,9 @@
  22                 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
  23
  24  #define PCIE_MISC_HARD_PCIE_HARD_DEBUG                                 0x4204
  25 -#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK       0x2
  26 -#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK               0x08000000
  27 +#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK       BIT(1)
  28 +#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK                BIT(21)
  29 +#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK               BIT(27)
  30
  31  #define PCIE_MSI_INTR2_STATUS                          0x4500
  32  #define PCIE_MSI_INTR2_CLR                             0x4508
  33 @@ -170,6 +171,7 @@ struct brcm_pcie {
  34         struct pci_bus          *root_bus;
  35         struct device_node      *np;
  36         bool                    ssc;
  37 +       bool                    l1ss;
  38         int                     gen;
  39         u64                     msi_target_addr;
  40         struct brcm_msi         *msi;
  41 @@ -834,12 +836,25 @@ static int brcm_pcie_setup(struct brcm_p
  42                 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
  43         writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
  44
  45 -       /*
  46 -        * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
  47 -        * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
  48 -        */
  49         tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  50 -       tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
  51 +       if (pcie->l1ss) {
  52 +               /*
  53 +                * Enable CLKREQ# signalling include L1 Substate control of
  54 +                * the CLKREQ# signal and the external reference clock buffer.
  55 +                * meet requirement for Endpoints that require CLKREQ#
  56 +                * assertion to clock active within 400ns.
  57 +                */
  58 +               tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
  59 +               tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
  60 +       } else {
  61 +               /*
  62 +                * Refclk from RC should be gated with CLKREQ# input when
  63 +                * ASPM L0s,L1 is enabled => setting the CLKREQ_DEBUG_ENABLE
  64 +                * field to 1.
  65 +                */
  66 +               tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
  67 +               tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
  68 +       }
  69         writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
  70
  71         return 0;
  72 @@ -944,6 +959,7 @@ static int brcm_pcie_probe(struct platfo
  73         pcie->gen = (ret < 0) ? 0 : ret;
  74
  75         pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
  76 +       pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss");
  77
  78         ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
  79                                               &bridge->dma_ranges, NULL);