target/linux/bcm27xx/patches-5.4/950-0714-vc4_hdmi_regs-Add-Intr2-register-block.patch

   1 From 2aa3a92e409ed4ad416eceacef998f0027016a81 Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Thu, 7 May 2020 18:16:07 +0100
   4 Subject: [PATCH] vc4_hdmi_regs: Add Intr2 register block
   5
   6 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
   7 ---
   8  arch/arm/boot/dts/bcm2711.dtsi      | 14 ++++++++++----
   9  drivers/gpu/drm/vc4/vc4_hdmi.c      |  8 ++++++++
  10  drivers/gpu/drm/vc4/vc4_hdmi.h      |  2 ++
  11  drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 17 +++++++++++++++++
  12  4 files changed, 37 insertions(+), 4 deletions(-)
  13
  14 --- a/arch/arm/boot/dts/bcm2711.dtsi
  15 +++ b/arch/arm/boot/dts/bcm2711.dtsi
  16 @@ -316,7 +316,8 @@
  17                               <0x7ef01f00 0x400>,
  18                               <0x7ef00200 0x80>,
  19                               <0x7ef04300 0x100>,
  20 -                             <0x7ef20000 0x100>;
  21 +                             <0x7ef20000 0x100>,
  22 +                             <0x7ef00100 0x30>;
  23                         reg-names = "hdmi",
  24                                     "dvp",
  25                                     "phy",
  26 @@ -325,13 +326,15 @@
  27                                     "metadata",
  28                                     "csc",
  29                                     "cec",
  30 -                                   "hd";
  31 +                                   "hd",
  32 +                                   "intr2";
  33                         clocks = <&firmware_clocks 13>;
  34                         clock-names = "hdmi";
  35                         resets = <&dvp 0>;
  36                         ddc = <&ddc0>;
  37                         dmas = <&dma 10>;
  38                         dma-names = "audio-rx";
  39 +                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  40                         status = "disabled";
  41                 };
  42
  43 @@ -353,7 +356,8 @@
  44                               <0x7ef06f00 0x400>,
  45                               <0x7ef00280 0x80>,
  46                               <0x7ef09300 0x100>,
  47 -                             <0x7ef20000 0x100>;
  48 +                             <0x7ef20000 0x100>,
  49 +                             <0x7ef00100 0x30>;
  50                         reg-names = "hdmi",
  51                                     "dvp",
  52                                     "phy",
  53 @@ -362,13 +366,15 @@
  54                                     "metadata",
  55                                     "csc",
  56                                     "cec",
  57 -                                   "hd";
  58 +                                   "hd",
  59 +                                   "intr2";
  60                         ddc = <&ddc1>;
  61                         clocks = <&firmware_clocks 13>;
  62                         clock-names = "hdmi";
  63                         resets = <&dvp 1>;
  64                         dmas = <&dma 17>;
  65                         dma-names = "audio-rx";
  66 +                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  67                         status = "disabled";
  68                 };
  69
  70 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  71 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  72 @@ -1581,6 +1581,14 @@ static int vc5_hdmi_init_resources(struc
  73         if (IS_ERR(vc4_hdmi->dvp_regs))
  74                 return PTR_ERR(vc4_hdmi->dvp_regs);
  75
  76 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr2");
  77 +       if (!res)
  78 +               return -ENODEV;
  79 +
  80 +       vc4_hdmi->intr2_regs = devm_ioremap(dev, res->start, resource_size(res));
  81 +       if (IS_ERR(vc4_hdmi->intr2_regs))
  82 +               return PTR_ERR(vc4_hdmi->intr2_regs);
  83 +
  84         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
  85         if (!res)
  86                 return -ENODEV;
  87 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
  88 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
  89 @@ -140,6 +140,8 @@ struct vc4_hdmi {
  90         void __iomem *ram_regs;
  91         /* VC5 Only */
  92         void __iomem *rm_regs;
  93 +       /* VC5 Only */
  94 +       void __iomem *intr2_regs;
  95
  96         int hpd_gpio;
  97         bool hpd_active_low;
  98 --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
  99 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
 100 @@ -24,6 +24,7 @@ enum vc4_hdmi_regs {
 101         VC5_PHY,
 102         VC5_RAM,
 103         VC5_RM,
 104 +       VC5_INTR2,
 105  };
 106
 107  enum vc4_hdmi_field {
 108 @@ -148,6 +149,7 @@ struct vc4_hdmi_register {
 109  #define VC5_CEC_REG(reg, offset)       _VC4_REG(VC5_CEC, reg, offset)
 110  #define VC5_CSC_REG(reg, offset)       _VC4_REG(VC5_CSC, reg, offset)
 111  #define VC5_DVP_REG(reg, offset)       _VC4_REG(VC5_DVP, reg, offset)
 112 +#define VC5_INTR2_REG(reg, offset)     _VC4_REG(VC5_INTR2, reg, offset)
 113  #define VC5_PHY_REG(reg, offset)       _VC4_REG(VC5_PHY, reg, offset)
 114  #define VC5_RAM_REG(reg, offset)       _VC4_REG(VC5_RAM, reg, offset)
 115  #define VC5_RM_REG(reg, offset)                _VC4_REG(VC5_RM, reg, offset)
 116 @@ -280,6 +282,12 @@ static const struct vc4_hdmi_register vc
 117         VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
 118         VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
 119         VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
 120 +       VC5_INTR2_REG(HDMI_CEC_CPU_STATUS, 0x0000),
 121 +       VC5_INTR2_REG(HDMI_CEC_CPU_SET, 0x0004),
 122 +       VC5_INTR2_REG(HDMI_CEC_CPU_CLEAR, 0x0008),
 123 +       VC5_INTR2_REG(HDMI_CEC_CPU_MASK_STATUS, 0x000c),
 124 +       VC5_INTR2_REG(HDMI_CEC_CPU_MASK_SET, 0x0010),
 125 +       VC5_INTR2_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0014),
 126
 127         VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
 128         VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
 129 @@ -356,6 +364,12 @@ static const struct vc4_hdmi_register vc
 130         VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
 131         VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
 132         VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
 133 +       VC5_INTR2_REG(HDMI_CEC_CPU_STATUS, 0x0000),
 134 +       VC5_INTR2_REG(HDMI_CEC_CPU_SET, 0x0004),
 135 +       VC5_INTR2_REG(HDMI_CEC_CPU_CLEAR, 0x0008),
 136 +       VC5_INTR2_REG(HDMI_CEC_CPU_MASK_STATUS, 0x000c),
 137 +       VC5_INTR2_REG(HDMI_CEC_CPU_MASK_SET, 0x0010),
 138 +       VC5_INTR2_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0014),
 139
 140         VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
 141         VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
 142 @@ -386,6 +400,9 @@ void __iomem *__vc4_hdmi_get_field_base(
 143         case VC5_DVP:
 144                 return hdmi->dvp_regs;
 145
 146 +       case VC5_INTR2:
 147 +               return hdmi->intr2_regs;
 148 +
 149         case VC5_PHY:
 150                 return hdmi->phy_regs;
 151