target/linux/bcm27xx/patches-5.4/950-0599-ARM-dts-bcm2711-Enable-the-display-pipeline.patch

   1 From 661edd663841d94bded4e95acfd0a4947cb079b5 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Wed, 12 Feb 2020 12:26:40 +0100
   4 Subject: [PATCH] ARM: dts: bcm2711: Enable the display pipeline
   5
   6 Now that all the drivers have been adjusted for it, let's bring in the
   7 necessary device tree changes.
   8
   9 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  10 ---
  11  arch/arm/boot/dts/bcm2711-rpi-4-b.dts |  40 ++++++++++
  12  arch/arm/boot/dts/bcm2711.dtsi        | 110 ++++++++++++++++++++++++++
  13  2 files changed, 150 insertions(+)
  14
  15 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
  16 +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
  17 @@ -138,6 +138,46 @@
  18         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  19  };
  20
  21 +&vc4 {
  22 +       status = "okay";
  23 +};
  24 +
  25 +&pixelvalve0 {
  26 +       status = "okay";
  27 +};
  28 +
  29 +&pixelvalve1 {
  30 +       status = "okay";
  31 +};
  32 +
  33 +&pixelvalve2 {
  34 +       status = "okay";
  35 +};
  36 +
  37 +&pixelvalve3 {
  38 +       status = "okay";
  39 +};
  40 +
  41 +&pixelvalve4 {
  42 +       status = "okay";
  43 +};
  44 +
  45 +&hdmi0 {
  46 +       status = "okay";
  47 +};
  48 +
  49 +&ddc0 {
  50 +       status = "okay";
  51 +};
  52 +
  53 +&hdmi1 {
  54 +       status = "okay";
  55 +};
  56 +
  57 +&ddc1 {
  58 +       status = "okay";
  59 +};
  60 +
  61  // =============================================
  62  // Downstream rpi- changes
  63
  64 --- a/arch/arm/boot/dts/bcm2711.dtsi
  65 +++ b/arch/arm/boot/dts/bcm2711.dtsi
  66 @@ -31,6 +31,11 @@
  67                 };
  68         };
  69
  70 +       vc4: gpu {
  71 +               compatible = "brcm,bcm2711-vc5";
  72 +               status = "disabled";
  73 +       };
  74 +
  75         clk_108MHz: clk-108M {
  76                 #clock-cells = <0>;
  77                 compatible = "fixed-clock";
  78 @@ -254,6 +259,27 @@
  79                         status = "disabled";
  80                 };
  81
  82 +               pixelvalve0: pixelvalve@7e206000 {
  83 +                       compatible = "brcm,bcm2711-pixelvalve0";
  84 +                       reg = <0x7e206000 0x100>;
  85 +                       interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  86 +                       status = "disabled";
  87 +               };
  88 +
  89 +               pixelvalve1: pixelvalve@7e207000 {
  90 +                       compatible = "brcm,bcm2711-pixelvalve1";
  91 +                       reg = <0x7e207000 0x100>;
  92 +                       interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  93 +                       status = "disabled";
  94 +               };
  95 +
  96 +               pixelvalve2: pixelvalve@7e20a000 {
  97 +                       compatible = "brcm,bcm2711-pixelvalve2";
  98 +                       reg = <0x7e20a000 0x100>;
  99 +                       interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 100 +                       status = "disabled";
 101 +               };
 102 +
 103                 pwm1: pwm@7e20c800 {
 104                         compatible = "brcm,bcm2835-pwm";
 105                         reg = <0x7e20c800 0x28>;
 106 @@ -264,6 +290,13 @@
 107                         status = "disabled";
 108                 };
 109
 110 +               pixelvalve4: pixelvalve@7e216000 {
 111 +                       compatible = "brcm,bcm2711-pixelvalve4";
 112 +                       reg = <0x7e216000 0x100>;
 113 +                       interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 114 +                       status = "disabled";
 115 +               };
 116 +
 117                 emmc2: emmc2@7e340000 {
 118                         compatible = "brcm,bcm2711-emmc2";
 119                         reg = <0x7e340000 0x100>;
 120 @@ -276,6 +309,13 @@
 121                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 122                 };
 123
 124 +               pixelvalve3: pixelvalve@7ec12000 {
 125 +                       compatible = "brcm,bcm2711-pixelvalve3";
 126 +                       reg = <0x7ec12000 0x100>;
 127 +                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 128 +                       status = "disabled";
 129 +               };
 130 +
 131                 dvp: clock@7ef00000 {
 132                         compatible = "brcm,brcm2711-dvp";
 133                         reg = <0x7ef00000 0x10>;
 134 @@ -283,6 +323,76 @@
 135                         #clock-cells = <1>;
 136                         #reset-cells = <1>;
 137                 };
 138 +
 139 +               hdmi0: hdmi@7ef00700 {
 140 +                       compatible = "brcm,bcm2711-hdmi0";
 141 +                       reg = <0x7ef00700 0x300>,
 142 +                             <0x7ef00300 0x200>,
 143 +                             <0x7ef00f00 0x80>,
 144 +                             <0x7ef00f80 0x80>,
 145 +                             <0x7ef01b00 0x200>,
 146 +                             <0x7ef01f00 0x400>,
 147 +                             <0x7ef00200 0x80>,
 148 +                             <0x7ef04300 0x100>,
 149 +                             <0x7ef20000 0x100>;
 150 +                       reg-names = "hdmi",
 151 +                                   "dvp",
 152 +                                   "phy",
 153 +                                   "rm",
 154 +                                   "packet",
 155 +                                   "metadata",
 156 +                                   "csc",
 157 +                                   "cec",
 158 +                                   "hd";
 159 +                       clocks = <&firmware_clocks 13>;
 160 +                       clock-names = "hdmi";
 161 +                       resets = <&dvp 0>;
 162 +                       ddc = <&ddc0>;
 163 +                       status = "disabled";
 164 +               };
 165 +
 166 +               ddc0: i2c@7ef04500 {
 167 +                       compatible = "brcm,bcm2711-hdmi-i2c";
 168 +                       reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
 169 +                       reg-names = "bsc", "auto-i2c";
 170 +                       clock-frequency = <390000>;
 171 +                       status = "disabled";
 172 +               };
 173 +
 174 +               hdmi1: hdmi@7ef05700 {
 175 +                       compatible = "brcm,bcm2711-hdmi1";
 176 +                       reg = <0x7ef05700 0x300>,
 177 +                             <0x7ef05300 0x200>,
 178 +                             <0x7ef05f00 0x80>,
 179 +                             <0x7ef05f80 0x80>,
 180 +                             <0x7ef06b00 0x200>,
 181 +                             <0x7ef06f00 0x400>,
 182 +                             <0x7ef00280 0x80>,
 183 +                             <0x7ef09300 0x100>,
 184 +                             <0x7ef20000 0x100>;
 185 +                       reg-names = "hdmi",
 186 +                                   "dvp",
 187 +                                   "phy",
 188 +                                   "rm",
 189 +                                   "packet",
 190 +                                   "metadata",
 191 +                                   "csc",
 192 +                                   "cec",
 193 +                                   "hd";
 194 +                       ddc = <&ddc1>;
 195 +                       clocks = <&firmware_clocks 13>;
 196 +                       clock-names = "hdmi";
 197 +                       resets = <&dvp 1>;
 198 +                       status = "disabled";
 199 +               };
 200 +
 201 +               ddc1: i2c@7ef09500 {
 202 +                       compatible = "brcm,bcm2711-hdmi-i2c";
 203 +                       reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
 204 +                       reg-names = "bsc", "auto-i2c";
 205 +                       clock-frequency = <390000>;
 206 +                       status = "disabled";
 207 +               };
 208         };
 209
 210         arm-pmu {