target/linux/bcm27xx/patches-5.4/950-0588-drm-vc4-hdmi-Add-a-set_timings-callback.patch

   1 From b9c57901c600e09b100942b637c6bb01e52b7326 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Mon, 6 Jan 2020 13:43:27 +0100
   4 Subject: [PATCH] drm/vc4: hdmi: Add a set_timings callback
   5
   6 Similarly to the previous patches, the timings setup in the HDMI controller
   7 of the BCM2711 is slightly different, mostly because it supports higher
   8 resolutions and thus needed more spaces for the various timings, resulting
   9 in the register layout changing.
  10
  11 Let's add a callback for that as well.
  12
  13 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  14 ---
  15  drivers/gpu/drm/vc4/vc4_hdmi.c | 71 +++++++++++++++++++---------------
  16  drivers/gpu/drm/vc4/vc4_hdmi.h |  4 ++
  17  2 files changed, 44 insertions(+), 31 deletions(-)
  18
  19 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  20 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  21 @@ -372,12 +372,9 @@ static void vc4_hdmi_csc_setup(struct vc
  22         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
  23  }
  24
  25 -static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
  26 +static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
  27 +                                struct drm_display_mode *mode)
  28  {
  29 -       struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
  30 -       struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
  31 -       struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
  32 -       bool debug_dump_regs = false;
  33         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
  34         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
  35         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
  36 @@ -395,6 +392,41 @@ static void vc4_hdmi_encoder_enable(stru
  37                                         mode->crtc_vsync_end -
  38                                         interlaced,
  39                                         VC4_HDMI_VERTB_VBP));
  40 +
  41 +       HDMI_WRITE(HDMI_HORZA,
  42 +                  (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
  43 +                  (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
  44 +                  VC4_SET_FIELD(mode->hdisplay * pixel_rep,
  45 +                                VC4_HDMI_HORZA_HAP));
  46 +
  47 +       HDMI_WRITE(HDMI_HORZB,
  48 +                  VC4_SET_FIELD((mode->htotal -
  49 +                                 mode->hsync_end) * pixel_rep,
  50 +                                VC4_HDMI_HORZB_HBP) |
  51 +                  VC4_SET_FIELD((mode->hsync_end -
  52 +                                 mode->hsync_start) * pixel_rep,
  53 +                                VC4_HDMI_HORZB_HSP) |
  54 +                  VC4_SET_FIELD((mode->hsync_start -
  55 +                                 mode->hdisplay) * pixel_rep,
  56 +                                VC4_HDMI_HORZB_HFP));
  57 +
  58 +       HDMI_WRITE(HDMI_VERTA0, verta);
  59 +       HDMI_WRITE(HDMI_VERTA1, verta);
  60 +
  61 +       HDMI_WRITE(HDMI_VERTB0, vertb_even);
  62 +       HDMI_WRITE(HDMI_VERTB1, vertb);
  63 +
  64 +       HDMI_WRITE(HDMI_VID_CTL,
  65 +                (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
  66 +                (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
  67 +}
  68 +
  69 +static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
  70 +{
  71 +       struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
  72 +       struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
  73 +       struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
  74 +       bool debug_dump_regs = false;
  75         int ret;
  76
  77         ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
  78 @@ -438,32 +470,8 @@ static void vc4_hdmi_encoder_enable(stru
  79                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
  80                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
  81
  82 -       HDMI_WRITE(HDMI_HORZA,
  83 -                  (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
  84 -                  (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
  85 -                  VC4_SET_FIELD(mode->hdisplay * pixel_rep,
  86 -                                VC4_HDMI_HORZA_HAP));
  87 -
  88 -       HDMI_WRITE(HDMI_HORZB,
  89 -                  VC4_SET_FIELD((mode->htotal -
  90 -                                 mode->hsync_end) * pixel_rep,
  91 -                                VC4_HDMI_HORZB_HBP) |
  92 -                  VC4_SET_FIELD((mode->hsync_end -
  93 -                                 mode->hsync_start) * pixel_rep,
  94 -                                VC4_HDMI_HORZB_HSP) |
  95 -                  VC4_SET_FIELD((mode->hsync_start -
  96 -                                 mode->hdisplay) * pixel_rep,
  97 -                                VC4_HDMI_HORZB_HFP));
  98 -
  99 -       HDMI_WRITE(HDMI_VERTA0, verta);
 100 -       HDMI_WRITE(HDMI_VERTA1, verta);
 101 -
 102 -       HDMI_WRITE(HDMI_VERTB0, vertb_even);
 103 -       HDMI_WRITE(HDMI_VERTB1, vertb);
 104 -
 105 -       HDMI_WRITE(HDMI_VID_CTL,
 106 -                (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 107 -                (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 108 +       if (vc4_hdmi->variant->set_timings)
 109 +               vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
 110
 111         if (vc4_encoder->hdmi_monitor &&
 112             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
 113 @@ -1440,6 +1448,7 @@ static const struct vc4_hdmi_variant bcm
 114         .init_resources         = vc4_hdmi_init_resources,
 115         .csc_setup              = vc4_hdmi_csc_setup,
 116         .reset                  = vc4_hdmi_reset,
 117 +       .set_timings            = vc4_hdmi_set_timings,
 118         .phy_init               = vc4_hdmi_phy_init,
 119         .phy_disable            = vc4_hdmi_phy_disable,
 120         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
 121 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
 122 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
 123 @@ -44,6 +44,10 @@ struct vc4_hdmi_variant {
 124         /* Callback to enable / disable the CSC */
 125         void (*csc_setup)(struct vc4_hdmi *vc4_hdmi, bool enable);
 126
 127 +       /* Callback to configure the video timings in the HDMI block */
 128 +       void (*set_timings)(struct vc4_hdmi *vc4_hdmi,
 129 +                           struct drm_display_mode *mode);
 130 +
 131         /* Callback to initialize the PHY according to the mode */
 132         void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
 133                          struct drm_display_mode *mode);