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[openwrt/openwrt.git] / target / linux / bcm27xx / patches-5.4 / 950-0539-drm-vc4-drv-Add-support-for-the-BCM2711-HVS5.patch
1 From 354d70a82947041b3d7b87f69641a6741febfc95 Mon Sep 17 00:00:00 2001
2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
3 Date: Thu, 8 Aug 2019 17:51:07 +0100
4 Subject: [PATCH] drm/vc4: drv: Add support for the BCM2711 HVS5
5
6 The HVS found in the BCM2711 is slightly different from the previous
7 generations.
8
9 Most notably, the display list layout changes a bit, the LBM doesn't have
10 the same size and the formats ordering for some formats is swapped.
11
12 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
13 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
14 ---
15 drivers/gpu/drm/vc4/vc4_crtc.c | 24 +++-
16 drivers/gpu/drm/vc4/vc4_drv.h | 4 +
17 drivers/gpu/drm/vc4/vc4_hvs.c | 17 ++-
18 drivers/gpu/drm/vc4/vc4_plane.c | 194 +++++++++++++++++++++++---------
19 drivers/gpu/drm/vc4/vc4_regs.h | 67 +++++++++++
20 5 files changed, 247 insertions(+), 59 deletions(-)
21
22 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
23 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
24 @@ -550,6 +550,7 @@ static void vc4_crtc_atomic_enable(struc
25 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
26 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
27 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
28 + u32 dispctrl;
29
30 require_hvs_enabled(dev);
31
32 @@ -564,11 +565,24 @@ static void vc4_crtc_atomic_enable(struc
33 * When feeding the transposer, we should operate in oneshot
34 * mode.
35 */
36 - HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
37 - VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
38 - VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
39 - SCALER_DISPCTRLX_ENABLE |
40 - (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
41 + dispctrl = SCALER_DISPCTRLX_ENABLE;
42 +
43 + if (!vc4->hvs->hvs5)
44 + dispctrl |= VC4_SET_FIELD(mode->hdisplay,
45 + SCALER_DISPCTRLX_WIDTH) |
46 + VC4_SET_FIELD(mode->vdisplay,
47 + SCALER_DISPCTRLX_HEIGHT) |
48 + (vc4_state->feed_txp ?
49 + SCALER_DISPCTRLX_ONESHOT : 0);
50 + else
51 + dispctrl |= VC4_SET_FIELD(mode->hdisplay,
52 + SCALER5_DISPCTRLX_WIDTH) |
53 + VC4_SET_FIELD(mode->vdisplay,
54 + SCALER5_DISPCTRLX_HEIGHT) |
55 + (vc4_state->feed_txp ?
56 + SCALER5_DISPCTRLX_ONESHOT : 0);
57 +
58 + HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
59
60 /* When feeding the transposer block the pixelvalve is unneeded and
61 * should not be enabled.
62 --- a/drivers/gpu/drm/vc4/vc4_drv.h
63 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
64 @@ -336,7 +336,11 @@ struct vc4_hvs {
65 spinlock_t mm_lock;
66
67 struct drm_mm_node mitchell_netravali_filter;
68 +
69 struct debugfs_regset32 regset;
70 +
71 + /* HVS version 5 flag, therefore requires updated dlist structures */
72 + bool hvs5;
73 };
74
75 struct vc4_plane {
76 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
77 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
78 @@ -223,6 +223,7 @@ static int vc4_hvs_bind(struct device *d
79 struct vc4_hvs *hvs = NULL;
80 int ret;
81 u32 dispctrl;
82 + unsigned int hvs_version;
83
84 hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
85 if (!hvs)
86 @@ -238,7 +239,14 @@ static int vc4_hvs_bind(struct device *d
87 hvs->regset.regs = hvs_regs;
88 hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
89
90 - hvs->dlist = hvs->regs + SCALER_DLIST_START;
91 + hvs_version = readl(hvs->regs + SCALER_DISPLSTAT) >> 24;
92 + if (hvs_version >= 0x40)
93 + hvs->hvs5 = true;
94 +
95 + if (!hvs->hvs5)
96 + hvs->dlist = hvs->regs + SCALER_DLIST_START;
97 + else
98 + hvs->dlist = hvs->regs + SCALER5_DLIST_START;
99
100 spin_lock_init(&hvs->mm_lock);
101
102 @@ -256,7 +264,12 @@ static int vc4_hvs_bind(struct device *d
103 * between planes when they don't overlap on the screen, but
104 * for now we just allocate globally.
105 */
106 - drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
107 + if (!hvs->hvs5)
108 + /* 96kB */
109 + drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
110 + else
111 + /* 70k words */
112 + drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
113
114 /* Upload filter kernels. We only have the one for now, so we
115 * keep it around for the lifetime of the driver.
116 --- a/drivers/gpu/drm/vc4/vc4_plane.c
117 +++ b/drivers/gpu/drm/vc4/vc4_plane.c
118 @@ -32,45 +32,60 @@ static const struct hvs_format {
119 u32 drm; /* DRM_FORMAT_* */
120 u32 hvs; /* HVS_FORMAT_* */
121 u32 pixel_order;
122 + u32 pixel_order_hvs5;
123 } hvs_formats[] = {
124 {
125 - .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
126 + .drm = DRM_FORMAT_XRGB8888,
127 + .hvs = HVS_PIXEL_FORMAT_RGBA8888,
128 .pixel_order = HVS_PIXEL_ORDER_ABGR,
129 + .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
130 },
131 {
132 - .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
133 + .drm = DRM_FORMAT_ARGB8888,
134 + .hvs = HVS_PIXEL_FORMAT_RGBA8888,
135 .pixel_order = HVS_PIXEL_ORDER_ABGR,
136 + .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
137 },
138 {
139 - .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
140 + .drm = DRM_FORMAT_ABGR8888,
141 + .hvs = HVS_PIXEL_FORMAT_RGBA8888,
142 .pixel_order = HVS_PIXEL_ORDER_ARGB,
143 + .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
144 },
145 {
146 - .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
147 + .drm = DRM_FORMAT_XBGR8888,
148 + .hvs = HVS_PIXEL_FORMAT_RGBA8888,
149 .pixel_order = HVS_PIXEL_ORDER_ARGB,
150 + .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
151 },
152 {
153 - .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
154 + .drm = DRM_FORMAT_RGB565,
155 + .hvs = HVS_PIXEL_FORMAT_RGB565,
156 .pixel_order = HVS_PIXEL_ORDER_XRGB,
157 },
158 {
159 - .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
160 + .drm = DRM_FORMAT_BGR565,
161 + .hvs = HVS_PIXEL_FORMAT_RGB565,
162 .pixel_order = HVS_PIXEL_ORDER_XBGR,
163 },
164 {
165 - .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
166 + .drm = DRM_FORMAT_ARGB1555,
167 + .hvs = HVS_PIXEL_FORMAT_RGBA5551,
168 .pixel_order = HVS_PIXEL_ORDER_ABGR,
169 },
170 {
171 - .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
172 + .drm = DRM_FORMAT_XRGB1555,
173 + .hvs = HVS_PIXEL_FORMAT_RGBA5551,
174 .pixel_order = HVS_PIXEL_ORDER_ABGR,
175 },
176 {
177 - .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
178 + .drm = DRM_FORMAT_RGB888,
179 + .hvs = HVS_PIXEL_FORMAT_RGB888,
180 .pixel_order = HVS_PIXEL_ORDER_XRGB,
181 },
182 {
183 - .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
184 + .drm = DRM_FORMAT_BGR888,
185 + .hvs = HVS_PIXEL_FORMAT_RGB888,
186 .pixel_order = HVS_PIXEL_ORDER_XBGR,
187 },
188 {
189 @@ -836,35 +851,6 @@ static int vc4_plane_mode_set(struct drm
190 return -EINVAL;
191 }
192
193 - /* Control word */
194 - vc4_dlist_write(vc4_state,
195 - SCALER_CTL0_VALID |
196 - (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
197 - (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
198 - VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
199 - (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
200 - (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
201 - VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
202 - (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
203 - VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
204 - VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
205 -
206 - /* Position Word 0: Image Positions and Alpha Value */
207 - vc4_state->pos0_offset = vc4_state->dlist_count;
208 - vc4_dlist_write(vc4_state,
209 - VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
210 - VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
211 - VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
212 -
213 - /* Position Word 1: Scaled Image Dimensions. */
214 - if (!vc4_state->is_unity) {
215 - vc4_dlist_write(vc4_state,
216 - VC4_SET_FIELD(vc4_state->crtc_w,
217 - SCALER_POS1_SCL_WIDTH) |
218 - VC4_SET_FIELD(vc4_state->crtc_h,
219 - SCALER_POS1_SCL_HEIGHT));
220 - }
221 -
222 /* Don't waste cycles mixing with plane alpha if the set alpha
223 * is opaque or there is no per-pixel alpha information.
224 * In any case we use the alpha property value as the fixed alpha.
225 @@ -872,20 +858,120 @@ static int vc4_plane_mode_set(struct drm
226 mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
227 fb->format->has_alpha;
228
229 - /* Position Word 2: Source Image Size, Alpha */
230 - vc4_state->pos2_offset = vc4_state->dlist_count;
231 - vc4_dlist_write(vc4_state,
232 - VC4_SET_FIELD(fb->format->has_alpha ?
233 - SCALER_POS2_ALPHA_MODE_PIPELINE :
234 - SCALER_POS2_ALPHA_MODE_FIXED,
235 - SCALER_POS2_ALPHA_MODE) |
236 - (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
237 - (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
238 - VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
239 - VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
240 + if (!vc4->hvs->hvs5) {
241 + /* Control word */
242 + vc4_dlist_write(vc4_state,
243 + SCALER_CTL0_VALID |
244 + (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
245 + (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
246 + VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
247 + (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
248 + (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
249 + VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
250 + (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
251 + VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
252 + VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
253 +
254 + /* Position Word 0: Image Positions and Alpha Value */
255 + vc4_state->pos0_offset = vc4_state->dlist_count;
256 + vc4_dlist_write(vc4_state,
257 + VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
258 + VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
259 + VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
260 +
261 + /* Position Word 1: Scaled Image Dimensions. */
262 + if (!vc4_state->is_unity) {
263 + vc4_dlist_write(vc4_state,
264 + VC4_SET_FIELD(vc4_state->crtc_w,
265 + SCALER_POS1_SCL_WIDTH) |
266 + VC4_SET_FIELD(vc4_state->crtc_h,
267 + SCALER_POS1_SCL_HEIGHT));
268 + }
269 +
270 + /* Position Word 2: Source Image Size, Alpha */
271 + vc4_state->pos2_offset = vc4_state->dlist_count;
272 + vc4_dlist_write(vc4_state,
273 + VC4_SET_FIELD(fb->format->has_alpha ?
274 + SCALER_POS2_ALPHA_MODE_PIPELINE :
275 + SCALER_POS2_ALPHA_MODE_FIXED,
276 + SCALER_POS2_ALPHA_MODE) |
277 + (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
278 + (fb->format->has_alpha ?
279 + SCALER_POS2_ALPHA_PREMULT : 0) |
280 + VC4_SET_FIELD(vc4_state->src_w[0],
281 + SCALER_POS2_WIDTH) |
282 + VC4_SET_FIELD(vc4_state->src_h[0],
283 + SCALER_POS2_HEIGHT));
284
285 - /* Position Word 3: Context. Written by the HVS. */
286 - vc4_dlist_write(vc4_state, 0xc0c0c0c0);
287 + /* Position Word 3: Context. Written by the HVS. */
288 + vc4_dlist_write(vc4_state, 0xc0c0c0c0);
289 +
290 + } else {
291 + u32 hvs_pixel_order = format->pixel_order;
292 +
293 + if (format->pixel_order_hvs5)
294 + hvs_pixel_order = format->pixel_order_hvs5;
295 +
296 + /* Control word */
297 + vc4_dlist_write(vc4_state,
298 + SCALER_CTL0_VALID |
299 + (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
300 + (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
301 + VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
302 + (vc4_state->is_unity ?
303 + SCALER5_CTL0_UNITY : 0) |
304 + VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
305 + VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
306 + SCALER5_CTL0_ALPHA_EXPAND |
307 + SCALER5_CTL0_RGB_EXPAND);
308 +
309 + /* Position Word 0: Image Positions and Alpha Value */
310 + vc4_state->pos0_offset = vc4_state->dlist_count;
311 + vc4_dlist_write(vc4_state,
312 + (rotation & DRM_MODE_REFLECT_Y ?
313 + SCALER5_POS0_VFLIP : 0) |
314 + VC4_SET_FIELD(vc4_state->crtc_x,
315 + SCALER_POS0_START_X) |
316 + (rotation & DRM_MODE_REFLECT_X ?
317 + SCALER5_POS0_HFLIP : 0) |
318 + VC4_SET_FIELD(vc4_state->crtc_y,
319 + SCALER5_POS0_START_Y)
320 + );
321 +
322 + /* Control Word 2 */
323 + vc4_dlist_write(vc4_state,
324 + VC4_SET_FIELD(state->alpha >> 4,
325 + SCALER5_CTL2_ALPHA) |
326 + fb->format->has_alpha ?
327 + SCALER5_CTL2_ALPHA_PREMULT : 0 |
328 + (mix_plane_alpha ?
329 + SCALER5_CTL2_ALPHA_MIX : 0) |
330 + VC4_SET_FIELD(fb->format->has_alpha ?
331 + SCALER5_CTL2_ALPHA_MODE_PIPELINE :
332 + SCALER5_CTL2_ALPHA_MODE_FIXED,
333 + SCALER5_CTL2_ALPHA_MODE)
334 + );
335 +
336 + /* Position Word 1: Scaled Image Dimensions. */
337 + if (!vc4_state->is_unity) {
338 + vc4_dlist_write(vc4_state,
339 + VC4_SET_FIELD(vc4_state->crtc_w,
340 + SCALER_POS1_SCL_WIDTH) |
341 + VC4_SET_FIELD(vc4_state->crtc_h,
342 + SCALER_POS1_SCL_HEIGHT));
343 + }
344 +
345 + /* Position Word 2: Source Image Size */
346 + vc4_state->pos2_offset = vc4_state->dlist_count;
347 + vc4_dlist_write(vc4_state,
348 + VC4_SET_FIELD(vc4_state->src_w[0],
349 + SCALER5_POS2_WIDTH) |
350 + VC4_SET_FIELD(vc4_state->src_h[0],
351 + SCALER5_POS2_HEIGHT));
352 +
353 + /* Position Word 3: Context. Written by the HVS. */
354 + vc4_dlist_write(vc4_state, 0xc0c0c0c0);
355 + }
356
357
358 /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
359 @@ -1276,6 +1362,10 @@ static bool vc4_format_mod_supported(str
360 default:
361 return false;
362 }
363 + case DRM_FORMAT_RGBX1010102:
364 + case DRM_FORMAT_BGRX1010102:
365 + case DRM_FORMAT_RGBA1010102:
366 + case DRM_FORMAT_BGRA1010102:
367 case DRM_FORMAT_YUV422:
368 case DRM_FORMAT_YVU422:
369 case DRM_FORMAT_YUV420:
370 --- a/drivers/gpu/drm/vc4/vc4_regs.h
371 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
372 @@ -328,6 +328,20 @@
373 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
374 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
375
376 +# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
377 +# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
378 +/* Generates a single frame when VSTART is seen and stops at the last
379 + * pixel read from the FIFO.
380 + */
381 +# define SCALER5_DISPCTRLX_ONESHOT BIT(15)
382 +/* Processes a single context in the dlist and then task switch,
383 + * instead of an entire line.
384 + */
385 +# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
386 +# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
387 +# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
388 +# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
389 +
390 #define SCALER_DISPBKGND0 0x00000044
391 # define SCALER_DISPBKGND_AUTOHS BIT(31)
392 # define SCALER_DISPBKGND_INTERLACE BIT(30)
393 @@ -461,6 +475,8 @@
394 #define SCALER_DLIST_START 0x00002000
395 #define SCALER_DLIST_SIZE 0x00004000
396
397 +#define SCALER5_DLIST_START 0x00004000
398 +
399 #define VC4_HDMI_CORE_REV 0x000
400
401 #define VC4_HDMI_SW_RESET_CONTROL 0x004
402 @@ -826,6 +842,8 @@ enum hvs_pixel_format {
403 HVS_PIXEL_FORMAT_PALETTE = 13,
404 HVS_PIXEL_FORMAT_YUV444_RGB = 14,
405 HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
406 + HVS_PIXEL_FORMAT_RGBA1010102 = 16,
407 + HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
408 };
409
410 /* Note: the LSB is the rightmost character shown. Only valid for
411 @@ -880,6 +898,10 @@ enum hvs_pixel_format {
412 #define SCALER_CTL0_RGBA_EXPAND_MSB 2
413 #define SCALER_CTL0_RGBA_EXPAND_ROUND 3
414
415 +#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
416 +
417 +#define SCALER5_CTL0_RGB_EXPAND BIT(11)
418 +
419 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
420 #define SCALER_CTL0_SCL1_SHIFT 8
421
422 @@ -897,10 +919,13 @@ enum hvs_pixel_format {
423
424 /* Set to indicate no scaling. */
425 #define SCALER_CTL0_UNITY BIT(4)
426 +#define SCALER5_CTL0_UNITY BIT(15)
427
428 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
429 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
430
431 +#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
432 +
433 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
434 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24
435
436 @@ -910,12 +935,48 @@ enum hvs_pixel_format {
437 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
438 #define SCALER_POS0_START_X_SHIFT 0
439
440 +#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
441 +#define SCALER5_POS0_START_Y_SHIFT 16
442 +
443 +#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
444 +#define SCALER5_POS0_START_X_SHIFT 0
445 +
446 +#define SCALER5_POS0_VFLIP BIT(31)
447 +#define SCALER5_POS0_HFLIP BIT(15)
448 +
449 +#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
450 +#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
451 +#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
452 +#define SCALER5_CTL2_ALPHA_MODE_FIXED 1
453 +#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
454 +#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
455 +
456 +#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
457 +
458 +#define SCALER5_CTL2_ALPHA_MIX BIT(28)
459 +
460 +#define SCALER5_CTL2_ALPHA_LOC BIT(25)
461 +
462 +#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
463 +#define SCALER5_CTL2_MAP_SEL_SHIFT 17
464 +
465 +#define SCALER5_CTL2_GAMMA BIT(16)
466 +
467 +#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
468 +#define SCALER5_CTL2_ALPHA_SHIFT 4
469 +
470 #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
471 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16
472
473 #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
474 #define SCALER_POS1_SCL_WIDTH_SHIFT 0
475
476 +#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
477 +#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
478 +
479 +#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
480 +#define SCALER5_POS1_SCL_WIDTH_SHIFT 0
481 +
482 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
483 #define SCALER_POS2_ALPHA_MODE_SHIFT 30
484 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0
485 @@ -931,6 +992,12 @@ enum hvs_pixel_format {
486 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
487 #define SCALER_POS2_WIDTH_SHIFT 0
488
489 +#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
490 +#define SCALER5_POS2_HEIGHT_SHIFT 16
491 +
492 +#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
493 +#define SCALER5_POS2_WIDTH_SHIFT 0
494 +
495 /* Color Space Conversion words. Some values are S2.8 signed
496 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
497 * 0x2: 2, 0x3: -1}
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