target/linux/bcm27xx/patches-5.4/950-0530-clk-bcm-rpi-Split-pllb-clock-hooks.patch

   1 From e2537b383e247198347e7124876b9ead531dbeef Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Fri, 7 Feb 2020 16:14:18 +0100
   4 Subject: [PATCH] clk: bcm: rpi: Split pllb clock hooks
   5
   6 The driver only supports the pllb for now and all the clock framework hooks
   7 are a mix of the generic firmware interface and the specifics of the pllb.
   8 Since we will support more clocks in the future let's split the generic and
   9 specific hooks
  10
  11 Cc: Michael Turquette <mturquette@baylibre.com>
  12 Cc: linux-clk@vger.kernel.org
  13 Reviewed-by: Stephen Boyd <sboyd@kernel.org>
  14 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  15 ---
  16  drivers/clk/bcm/clk-raspberrypi.c | 30 ++++++++++++++++++++++--------
  17  1 file changed, 22 insertions(+), 8 deletions(-)
  18
  19 --- a/drivers/clk/bcm/clk-raspberrypi.c
  20 +++ b/drivers/clk/bcm/clk-raspberrypi.c
  21 @@ -104,8 +104,8 @@ static int raspberrypi_fw_is_prepared(st
  22  }
  23
  24
  25 -static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
  26 -                                                unsigned long parent_rate)
  27 +static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,
  28 +                                            unsigned long parent_rate)
  29  {
  30         struct raspberrypi_clk_data *data =
  31                 container_of(hw, struct raspberrypi_clk_data, hw);
  32 @@ -118,21 +118,27 @@ static unsigned long raspberrypi_fw_pll_
  33         if (ret)
  34                 return ret;
  35
  36 -       return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
  37 +       return val;
  38  }
  39
  40 -static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  41 -                                      unsigned long parent_rate)
  42 +static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
  43 +                                                unsigned long parent_rate)
  44 +{
  45 +       return raspberrypi_fw_get_rate(hw, parent_rate) *
  46 +               RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
  47 +}
  48 +
  49 +static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
  50 +                                  unsigned long parent_rate)
  51  {
  52         struct raspberrypi_clk_data *data =
  53                 container_of(hw, struct raspberrypi_clk_data, hw);
  54         struct raspberrypi_clk *rpi = data->rpi;
  55 -       u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
  56 +       u32 _rate = rate;
  57         int ret;
  58
  59         ret = raspberrypi_clock_property(rpi->firmware, data,
  60 -                                        RPI_FIRMWARE_SET_CLOCK_RATE,
  61 -                                        &new_rate);
  62 +                                        RPI_FIRMWARE_SET_CLOCK_RATE, &_rate);
  63         if (ret)
  64                 dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
  65                                     clk_hw_get_name(hw), ret);
  66 @@ -140,6 +146,14 @@ static int raspberrypi_fw_pll_set_rate(s
  67         return ret;
  68  }
  69
  70 +static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  71 +                                      unsigned long parent_rate)
  72 +{
  73 +       u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
  74 +
  75 +       return raspberrypi_fw_set_rate(hw, new_rate, parent_rate);
  76 +}
  77 +
  78  /*
  79   * Sadly there is no firmware rate rounding interface. We borrowed it from
  80   * clk-bcm2835.