target/linux/bcm27xx/patches-5.4/950-0460-PCI-brcmstb-Add-MSI-support.patch

   1 From 1a90ecdfae1c0cf1b242276f6f0e3d98b5877f14 Mon Sep 17 00:00:00 2001
   2 From: Jim Quinlan <james.quinlan@broadcom.com>
   3 Date: Mon, 16 Dec 2019 12:01:10 +0100
   4 Subject: [PATCH] PCI: brcmstb: Add MSI support
   5
   6 commit 40ca1bf580ef24df30702032ba5e40dfdcaa200b upstream.
   7
   8 This adds MSI support to the Broadcom STB PCIe host controller. The MSI
   9 controller is physically located within the PCIe block, however, there
  10 is no reason why the MSI controller could not be moved elsewhere in the
  11 future. MSIX is not supported by the HW.
  12
  13 Since the internal Brcmstb MSI controller is intertwined with the PCIe
  14 controller, it is not its own platform device but rather part of the
  15 PCIe platform device.
  16
  17 Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
  18 Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
  19 Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
  20 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  21 Reviewed-by: Marc Zyngier <maz@kernel.org>
  22 Reviewed-by: Andrew Murray <andrew.murray@arm.com>
  23 ---
  24  drivers/pci/controller/Kconfig        |   1 +
  25  drivers/pci/controller/pcie-brcmstb.c | 262 +++++++++++++++++++++++++-
  26  2 files changed, 262 insertions(+), 1 deletion(-)
  27
  28 --- a/drivers/pci/controller/Kconfig
  29 +++ b/drivers/pci/controller/Kconfig
  30 @@ -285,6 +285,7 @@ config PCIE_BRCMSTB
  31         tristate "Broadcom Brcmstb PCIe host controller"
  32         depends on ARCH_BCM2835 || COMPILE_TEST
  33         depends on OF
  34 +       depends on PCI_MSI_IRQ_DOMAIN
  35         help
  36           Say Y here to enable PCIe host controller support for
  37           Broadcom STB based SoCs, like the Raspberry Pi 4.
  38 --- a/drivers/pci/controller/pcie-brcmstb.c
  39 +++ b/drivers/pci/controller/pcie-brcmstb.c
  40 @@ -2,6 +2,7 @@
  41  /* Copyright (C) 2009 - 2019 Broadcom */
  42
  43  #include <linux/bitfield.h>
  44 +#include <linux/bitops.h>
  45  #include <linux/clk.h>
  46  #include <linux/compiler.h>
  47  #include <linux/delay.h>
  48 @@ -9,11 +10,13 @@
  49  #include <linux/interrupt.h>
  50  #include <linux/io.h>
  51  #include <linux/ioport.h>
  52 +#include <linux/irqchip/chained_irq.h>
  53  #include <linux/irqdomain.h>
  54  #include <linux/kernel.h>
  55  #include <linux/list.h>
  56  #include <linux/log2.h>
  57  #include <linux/module.h>
  58 +#include <linux/msi.h>
  59  #include <linux/of_address.h>
  60  #include <linux/of_irq.h>
  61  #include <linux/of_pci.h>
  62 @@ -67,6 +70,12 @@
  63  #define PCIE_MISC_RC_BAR3_CONFIG_LO                    0x403c
  64  #define  PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK         0x1f
  65
  66 +#define PCIE_MISC_MSI_BAR_CONFIG_LO                    0x4044
  67 +#define PCIE_MISC_MSI_BAR_CONFIG_HI                    0x4048
  68 +
  69 +#define PCIE_MISC_MSI_DATA_CONFIG                      0x404c
  70 +#define  PCIE_MISC_MSI_DATA_CONFIG_VAL                 0xffe06540
  71 +
  72  #define PCIE_MISC_PCIE_CTRL                            0x4064
  73  #define  PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK     0x1
  74
  75 @@ -114,6 +123,11 @@
  76
  77  /* PCIe parameters */
  78  #define BRCM_NUM_PCIE_OUT_WINS         0x4
  79 +#define BRCM_INT_PCI_MSI_NR            32
  80 +
  81 +/* MSI target adresses */
  82 +#define BRCM_MSI_TARGET_ADDR_LT_4GB    0x0fffffffcULL
  83 +#define BRCM_MSI_TARGET_ADDR_GT_4GB    0xffffffffcULL
  84
  85  /* MDIO registers */
  86  #define MDIO_PORT0                     0x0
  87 @@ -135,6 +149,19 @@
  88  #define SSC_STATUS_SSC_MASK            0x400
  89  #define SSC_STATUS_PLL_LOCK_MASK       0x800
  90
  91 +struct brcm_msi {
  92 +       struct device           *dev;
  93 +       void __iomem            *base;
  94 +       struct device_node      *np;
  95 +       struct irq_domain       *msi_domain;
  96 +       struct irq_domain       *inner_domain;
  97 +       struct mutex            lock; /* guards the alloc/free operations */
  98 +       u64                     target_addr;
  99 +       int                     irq;
 100 +       /* used indicates which MSI interrupts have been alloc'd */
 101 +       unsigned long           used;
 102 +};
 103 +
 104  /* Internal PCIe Host Controller Information.*/
 105  struct brcm_pcie {
 106         struct device           *dev;
 107 @@ -144,6 +171,8 @@ struct brcm_pcie {
 108         struct device_node      *np;
 109         bool                    ssc;
 110         int                     gen;
 111 +       u64                     msi_target_addr;
 112 +       struct brcm_msi         *msi;
 113  };
 114
 115  /*
 116 @@ -309,6 +338,215 @@ static void brcm_pcie_set_outbound_win(s
 117         writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
 118  }
 119
 120 +static struct irq_chip brcm_msi_irq_chip = {
 121 +       .name            = "BRCM STB PCIe MSI",
 122 +       .irq_ack         = irq_chip_ack_parent,
 123 +       .irq_mask        = pci_msi_mask_irq,
 124 +       .irq_unmask      = pci_msi_unmask_irq,
 125 +};
 126 +
 127 +static struct msi_domain_info brcm_msi_domain_info = {
 128 +       /* Multi MSI is supported by the controller, but not by this driver */
 129 +       .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
 130 +       .chip   = &brcm_msi_irq_chip,
 131 +};
 132 +
 133 +static void brcm_pcie_msi_isr(struct irq_desc *desc)
 134 +{
 135 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 136 +       unsigned long status, virq;
 137 +       struct brcm_msi *msi;
 138 +       struct device *dev;
 139 +       u32 bit;
 140 +
 141 +       chained_irq_enter(chip, desc);
 142 +       msi = irq_desc_get_handler_data(desc);
 143 +       dev = msi->dev;
 144 +
 145 +       status = readl(msi->base + PCIE_MSI_INTR2_STATUS);
 146 +       for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
 147 +               virq = irq_find_mapping(msi->inner_domain, bit);
 148 +               if (virq)
 149 +                       generic_handle_irq(virq);
 150 +               else
 151 +                       dev_dbg(dev, "unexpected MSI\n");
 152 +       }
 153 +
 154 +       chained_irq_exit(chip, desc);
 155 +}
 156 +
 157 +static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 158 +{
 159 +       struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
 160 +
 161 +       msg->address_lo = lower_32_bits(msi->target_addr);
 162 +       msg->address_hi = upper_32_bits(msi->target_addr);
 163 +       msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL) | data->hwirq;
 164 +}
 165 +
 166 +static int brcm_msi_set_affinity(struct irq_data *irq_data,
 167 +                                const struct cpumask *mask, bool force)
 168 +{
 169 +       return -EINVAL;
 170 +}
 171 +
 172 +static void brcm_msi_ack_irq(struct irq_data *data)
 173 +{
 174 +       struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
 175 +
 176 +       writel(1 << data->hwirq, msi->base + PCIE_MSI_INTR2_CLR);
 177 +}
 178 +
 179 +
 180 +static struct irq_chip brcm_msi_bottom_irq_chip = {
 181 +       .name                   = "BRCM STB MSI",
 182 +       .irq_compose_msi_msg    = brcm_msi_compose_msi_msg,
 183 +       .irq_set_affinity       = brcm_msi_set_affinity,
 184 +       .irq_ack                = brcm_msi_ack_irq,
 185 +};
 186 +
 187 +static int brcm_msi_alloc(struct brcm_msi *msi)
 188 +{
 189 +       int hwirq;
 190 +
 191 +       mutex_lock(&msi->lock);
 192 +       hwirq = bitmap_find_free_region(&msi->used, BRCM_INT_PCI_MSI_NR, 0);
 193 +       mutex_unlock(&msi->lock);
 194 +
 195 +       return hwirq;
 196 +}
 197 +
 198 +static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
 199 +{
 200 +       mutex_lock(&msi->lock);
 201 +       bitmap_release_region(&msi->used, hwirq, 0);
 202 +       mutex_unlock(&msi->lock);
 203 +}
 204 +
 205 +static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 206 +                                unsigned int nr_irqs, void *args)
 207 +{
 208 +       struct brcm_msi *msi = domain->host_data;
 209 +       int hwirq;
 210 +
 211 +       hwirq = brcm_msi_alloc(msi);
 212 +
 213 +       if (hwirq < 0)
 214 +               return hwirq;
 215 +
 216 +       irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
 217 +                           &brcm_msi_bottom_irq_chip, domain->host_data,
 218 +                           handle_edge_irq, NULL, NULL);
 219 +       return 0;
 220 +}
 221 +
 222 +static void brcm_irq_domain_free(struct irq_domain *domain,
 223 +                                unsigned int virq, unsigned int nr_irqs)
 224 +{
 225 +       struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 226 +       struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
 227 +
 228 +       brcm_msi_free(msi, d->hwirq);
 229 +}
 230 +
 231 +static const struct irq_domain_ops msi_domain_ops = {
 232 +       .alloc  = brcm_irq_domain_alloc,
 233 +       .free   = brcm_irq_domain_free,
 234 +};
 235 +
 236 +static int brcm_allocate_domains(struct brcm_msi *msi)
 237 +{
 238 +       struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
 239 +       struct device *dev = msi->dev;
 240 +
 241 +       msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR,
 242 +                                                 &msi_domain_ops, msi);
 243 +       if (!msi->inner_domain) {
 244 +               dev_err(dev, "failed to create IRQ domain\n");
 245 +               return -ENOMEM;
 246 +       }
 247 +
 248 +       msi->msi_domain = pci_msi_create_irq_domain(fwnode,
 249 +                                                   &brcm_msi_domain_info,
 250 +                                                   msi->inner_domain);
 251 +       if (!msi->msi_domain) {
 252 +               dev_err(dev, "failed to create MSI domain\n");
 253 +               irq_domain_remove(msi->inner_domain);
 254 +               return -ENOMEM;
 255 +       }
 256 +
 257 +       return 0;
 258 +}
 259 +
 260 +static void brcm_free_domains(struct brcm_msi *msi)
 261 +{
 262 +       irq_domain_remove(msi->msi_domain);
 263 +       irq_domain_remove(msi->inner_domain);
 264 +}
 265 +
 266 +static void brcm_msi_remove(struct brcm_pcie *pcie)
 267 +{
 268 +       struct brcm_msi *msi = pcie->msi;
 269 +
 270 +       if (!msi)
 271 +               return;
 272 +       irq_set_chained_handler(msi->irq, NULL);
 273 +       irq_set_handler_data(msi->irq, NULL);
 274 +       brcm_free_domains(msi);
 275 +}
 276 +
 277 +static void brcm_msi_set_regs(struct brcm_msi *msi)
 278 +{
 279 +       writel(0xffffffff, msi->base + PCIE_MSI_INTR2_MASK_CLR);
 280 +
 281 +       /*
 282 +        * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
 283 +        * enable, which we set to 1.
 284 +        */
 285 +       writel(lower_32_bits(msi->target_addr) | 0x1,
 286 +              msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
 287 +       writel(upper_32_bits(msi->target_addr),
 288 +              msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
 289 +
 290 +       writel(PCIE_MISC_MSI_DATA_CONFIG_VAL,
 291 +              msi->base + PCIE_MISC_MSI_DATA_CONFIG);
 292 +}
 293 +
 294 +static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
 295 +{
 296 +       struct brcm_msi *msi;
 297 +       int irq, ret;
 298 +       struct device *dev = pcie->dev;
 299 +
 300 +       irq = irq_of_parse_and_map(dev->of_node, 1);
 301 +       if (irq <= 0) {
 302 +               dev_err(dev, "cannot map MSI interrupt\n");
 303 +               return -ENODEV;
 304 +       }
 305 +
 306 +       msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
 307 +       if (!msi)
 308 +               return -ENOMEM;
 309 +
 310 +       mutex_init(&msi->lock);
 311 +       msi->dev = dev;
 312 +       msi->base = pcie->base;
 313 +       msi->np = pcie->np;
 314 +       msi->target_addr = pcie->msi_target_addr;
 315 +       msi->irq = irq;
 316 +
 317 +       ret = brcm_allocate_domains(msi);
 318 +       if (ret)
 319 +               return ret;
 320 +
 321 +       irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
 322 +
 323 +       brcm_msi_set_regs(msi);
 324 +       pcie->msi = msi;
 325 +
 326 +       return 0;
 327 +}
 328 +
 329  /* The controller is capable of serving in both RC and EP roles */
 330  static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
 331  {
 332 @@ -497,6 +735,18 @@ static int brcm_pcie_setup(struct brcm_p
 333                           PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK);
 334         writel(tmp, base + PCIE_MISC_MISC_CTRL);
 335
 336 +       /*
 337 +        * We ideally want the MSI target address to be located in the 32bit
 338 +        * addressable memory area. Some devices might depend on it. This is
 339 +        * possible either when the inbound window is located above the lower
 340 +        * 4GB or when the inbound area is smaller than 4GB (taking into
 341 +        * account the rounding-up we're forced to perform).
 342 +        */
 343 +       if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G)
 344 +               pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
 345 +       else
 346 +               pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
 347 +
 348         /* disable the PCIe->GISB memory window (RC_BAR1) */
 349         tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
 350         tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
 351 @@ -646,6 +896,7 @@ static void brcm_pcie_turn_off(struct br
 352
 353  static void __brcm_pcie_remove(struct brcm_pcie *pcie)
 354  {
 355 +       brcm_msi_remove(pcie);
 356         brcm_pcie_turn_off(pcie);
 357         clk_disable_unprepare(pcie->clk);
 358         clk_put(pcie->clk);
 359 @@ -664,7 +915,7 @@ static int brcm_pcie_remove(struct platf
 360
 361  static int brcm_pcie_probe(struct platform_device *pdev)
 362  {
 363 -       struct device_node *np = pdev->dev.of_node;
 364 +       struct device_node *np = pdev->dev.of_node, *msi_np;
 365         struct pci_host_bridge *bridge;
 366         struct brcm_pcie *pcie;
 367         struct pci_bus *child;
 368 @@ -708,6 +959,15 @@ static int brcm_pcie_probe(struct platfo
 369         if (ret)
 370                 goto fail;
 371
 372 +       msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
 373 +       if (pci_msi_enabled() && msi_np == pcie->np) {
 374 +               ret = brcm_pcie_enable_msi(pcie);
 375 +               if (ret) {
 376 +                       dev_err(pcie->dev, "probe of internal MSI failed");
 377 +                       goto fail;
 378 +               }
 379 +       }
 380 +
 381         bridge->dev.parent = &pdev->dev;
 382         bridge->busnr = 0;
 383         bridge->ops = &brcm_pcie_ops;