target/linux/bcm27xx/patches-5.4/950-0446-ARM-dts-bcm2711-Enable-PCIe-controller.patch

   1 From 0ec0bc884f6cf1ec9775c750f78ce28be7da4340 Mon Sep 17 00:00:00 2001
   2 From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
   3 Date: Mon, 16 Dec 2019 12:01:08 +0100
   4 Subject: [PATCH] ARM: dts: bcm2711: Enable PCIe controller
   5
   6 commit d5c8dc0d4c880fbde5293cc186b1ab23466254c4 upstream.
   7
   8 This enables bcm2711's PCIe bus, which is hardwired to a VIA
   9 Technologies XHCI USB 3.0 controller.
  10
  11 Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
  12 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  13 ---
  14  arch/arm/boot/dts/bcm2711.dtsi | 31 ++++++++++++++++++++++++++++++-
  15  1 file changed, 30 insertions(+), 1 deletion(-)
  16
  17 --- a/arch/arm/boot/dts/bcm2711.dtsi
  18 +++ b/arch/arm/boot/dts/bcm2711.dtsi
  19 @@ -331,7 +331,36 @@
  20                 #address-cells = <2>;
  21                 #size-cells = <1>;
  22
  23 -               ranges = <0x0 0x7c000000  0x0 0xfc000000  0x03800000>;
  24 +               ranges = <0x0 0x7c000000  0x0 0xfc000000  0x03800000>,
  25 +                        <0x6 0x00000000  0x6 0x00000000  0x40000000>;
  26 +
  27 +               pcie0: pcie@7d500000 {
  28 +                       compatible = "brcm,bcm2711-pcie";
  29 +                       reg = <0x0 0x7d500000 0x9310>;
  30 +                       device_type = "pci";
  31 +                       #address-cells = <3>;
  32 +                       #interrupt-cells = <1>;
  33 +                       #size-cells = <2>;
  34 +                       interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
  35 +                                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
  36 +                       interrupt-names = "pcie", "msi";
  37 +                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  38 +                       interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
  39 +                                                       IRQ_TYPE_LEVEL_HIGH>;
  40 +                       msi-controller;
  41 +                       msi-parent = <&pcie0>;
  42 +
  43 +                       ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
  44 +                                 0x0 0x04000000>;
  45 +                       /*
  46 +                        * The wrapper around the PCIe block has a bug
  47 +                        * preventing it from accessing beyond the first 3GB of
  48 +                        * memory.
  49 +                        */
  50 +                       dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
  51 +                                     0x0 0xc0000000>;
  52 +                       brcm,enable-ssc;
  53 +               };
  54
  55                 genet: ethernet@7d580000 {
  56                         compatible = "brcm,bcm2711-genet-v5";