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wwan: fix hotplug event handling
[openwrt/openwrt.git] / target / linux / bcm27xx / patches-5.4 / 950-0441-bcm2835-dma-Correct-SoC-name.patch
1 From f498861a16d0b9a189a329080da1aa64d6e9bda7 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.com>
3 Date: Fri, 31 Jan 2020 09:28:57 +0000
4 Subject: [PATCH] bcm2835-dma: Correct SoC name
5
6 The Pi 4 SoC is called BCM2711, not BCM2838.
7
8 Fixes: "bcm2835-dma: Add proper 40-bit DMA support"
9 ---
10 drivers/dma/bcm2835-dma.c | 274 +++++++++++++++++++-------------------
11 1 file changed, 137 insertions(+), 137 deletions(-)
12
13 --- a/drivers/dma/bcm2835-dma.c
14 +++ b/drivers/dma/bcm2835-dma.c
15 @@ -38,7 +38,7 @@
16 #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
17 #define BCM2835_DMA_CHAN_NAME_SIZE 8
18 #define BCM2835_DMA_BULK_MASK BIT(0)
19 -#define BCM2838_DMA_MEMCPY_CHAN 14
20 +#define BCM2711_DMA_MEMCPY_CHAN 14
21
22 struct bcm2835_dma_cfg_data {
23 u32 chan_40bit_mask;
24 @@ -70,7 +70,7 @@ struct bcm2835_dma_cb {
25 uint32_t pad[2];
26 };
27
28 -struct bcm2838_dma40_scb {
29 +struct bcm2711_dma40_scb {
30 uint32_t ti;
31 uint32_t src;
32 uint32_t srci;
33 @@ -200,98 +200,98 @@ struct bcm2835_desc {
34 #define MAX_LITE_DMA_LEN (SZ_64K - 4)
35
36 /* 40-bit DMA support */
37 -#define BCM2838_DMA40_CS 0x00
38 -#define BCM2838_DMA40_CB 0x04
39 -#define BCM2838_DMA40_DEBUG 0x0c
40 -#define BCM2838_DMA40_TI 0x10
41 -#define BCM2838_DMA40_SRC 0x14
42 -#define BCM2838_DMA40_SRCI 0x18
43 -#define BCM2838_DMA40_DEST 0x1c
44 -#define BCM2838_DMA40_DESTI 0x20
45 -#define BCM2838_DMA40_LEN 0x24
46 -#define BCM2838_DMA40_NEXT_CB 0x28
47 -#define BCM2838_DMA40_DEBUG2 0x2c
48 -
49 -#define BCM2838_DMA40_ACTIVE BIT(0)
50 -#define BCM2838_DMA40_END BIT(1)
51 -#define BCM2838_DMA40_INT BIT(2)
52 -#define BCM2838_DMA40_DREQ BIT(3) /* DREQ state */
53 -#define BCM2838_DMA40_RD_PAUSED BIT(4) /* Reading is paused */
54 -#define BCM2838_DMA40_WR_PAUSED BIT(5) /* Writing is paused */
55 -#define BCM2838_DMA40_DREQ_PAUSED BIT(6) /* Is paused by DREQ flow control */
56 -#define BCM2838_DMA40_WAITING_FOR_WRITES BIT(7) /* Waiting for last write */
57 -#define BCM2838_DMA40_ERR BIT(10)
58 -#define BCM2838_DMA40_QOS(x) (((x) & 0x1f) << 16)
59 -#define BCM2838_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20)
60 -#define BCM2838_DMA40_WAIT_FOR_WRITES BIT(28)
61 -#define BCM2838_DMA40_DISDEBUG BIT(29)
62 -#define BCM2838_DMA40_ABORT BIT(30)
63 -#define BCM2838_DMA40_HALT BIT(31)
64 -#define BCM2838_DMA40_CS_FLAGS(x) (x & (BCM2838_DMA40_QOS(15) | \
65 - BCM2838_DMA40_PANIC_QOS(15) | \
66 - BCM2838_DMA40_WAIT_FOR_WRITES | \
67 - BCM2838_DMA40_DISDEBUG))
68 +#define BCM2711_DMA40_CS 0x00
69 +#define BCM2711_DMA40_CB 0x04
70 +#define BCM2711_DMA40_DEBUG 0x0c
71 +#define BCM2711_DMA40_TI 0x10
72 +#define BCM2711_DMA40_SRC 0x14
73 +#define BCM2711_DMA40_SRCI 0x18
74 +#define BCM2711_DMA40_DEST 0x1c
75 +#define BCM2711_DMA40_DESTI 0x20
76 +#define BCM2711_DMA40_LEN 0x24
77 +#define BCM2711_DMA40_NEXT_CB 0x28
78 +#define BCM2711_DMA40_DEBUG2 0x2c
79 +
80 +#define BCM2711_DMA40_ACTIVE BIT(0)
81 +#define BCM2711_DMA40_END BIT(1)
82 +#define BCM2711_DMA40_INT BIT(2)
83 +#define BCM2711_DMA40_DREQ BIT(3) /* DREQ state */
84 +#define BCM2711_DMA40_RD_PAUSED BIT(4) /* Reading is paused */
85 +#define BCM2711_DMA40_WR_PAUSED BIT(5) /* Writing is paused */
86 +#define BCM2711_DMA40_DREQ_PAUSED BIT(6) /* Is paused by DREQ flow control */
87 +#define BCM2711_DMA40_WAITING_FOR_WRITES BIT(7) /* Waiting for last write */
88 +#define BCM2711_DMA40_ERR BIT(10)
89 +#define BCM2711_DMA40_QOS(x) (((x) & 0x1f) << 16)
90 +#define BCM2711_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20)
91 +#define BCM2711_DMA40_WAIT_FOR_WRITES BIT(28)
92 +#define BCM2711_DMA40_DISDEBUG BIT(29)
93 +#define BCM2711_DMA40_ABORT BIT(30)
94 +#define BCM2711_DMA40_HALT BIT(31)
95 +#define BCM2711_DMA40_CS_FLAGS(x) (x & (BCM2711_DMA40_QOS(15) | \
96 + BCM2711_DMA40_PANIC_QOS(15) | \
97 + BCM2711_DMA40_WAIT_FOR_WRITES | \
98 + BCM2711_DMA40_DISDEBUG))
99
100 /* Transfer information bits */
101 -#define BCM2838_DMA40_INTEN BIT(0)
102 -#define BCM2838_DMA40_TDMODE BIT(1) /* 2D-Mode */
103 -#define BCM2838_DMA40_WAIT_RESP BIT(2) /* wait for AXI write to be acked */
104 -#define BCM2838_DMA40_WAIT_RD_RESP BIT(3) /* wait for AXI read to complete */
105 -#define BCM2838_DMA40_PER_MAP(x) ((x & 31) << 9) /* REQ source */
106 -#define BCM2838_DMA40_S_DREQ BIT(14) /* enable SREQ for source */
107 -#define BCM2838_DMA40_D_DREQ BIT(15) /* enable DREQ for destination */
108 -#define BCM2838_DMA40_S_WAIT(x) ((x & 0xff) << 16) /* add DMA read-wait cycles */
109 -#define BCM2838_DMA40_D_WAIT(x) ((x & 0xff) << 24) /* add DMA write-wait cycles */
110 +#define BCM2711_DMA40_INTEN BIT(0)
111 +#define BCM2711_DMA40_TDMODE BIT(1) /* 2D-Mode */
112 +#define BCM2711_DMA40_WAIT_RESP BIT(2) /* wait for AXI write to be acked */
113 +#define BCM2711_DMA40_WAIT_RD_RESP BIT(3) /* wait for AXI read to complete */
114 +#define BCM2711_DMA40_PER_MAP(x) ((x & 31) << 9) /* REQ source */
115 +#define BCM2711_DMA40_S_DREQ BIT(14) /* enable SREQ for source */
116 +#define BCM2711_DMA40_D_DREQ BIT(15) /* enable DREQ for destination */
117 +#define BCM2711_DMA40_S_WAIT(x) ((x & 0xff) << 16) /* add DMA read-wait cycles */
118 +#define BCM2711_DMA40_D_WAIT(x) ((x & 0xff) << 24) /* add DMA write-wait cycles */
119
120 /* debug register bits */
121 -#define BCM2838_DMA40_DEBUG_WRITE_ERR BIT(0)
122 -#define BCM2838_DMA40_DEBUG_FIFO_ERR BIT(1)
123 -#define BCM2838_DMA40_DEBUG_READ_ERR BIT(2)
124 -#define BCM2838_DMA40_DEBUG_READ_CB_ERR BIT(3)
125 -#define BCM2838_DMA40_DEBUG_IN_ON_ERR BIT(8)
126 -#define BCM2838_DMA40_DEBUG_ABORT_ON_ERR BIT(9)
127 -#define BCM2838_DMA40_DEBUG_HALT_ON_ERR BIT(10)
128 -#define BCM2838_DMA40_DEBUG_DISABLE_CLK_GATE BIT(11)
129 -#define BCM2838_DMA40_DEBUG_RSTATE_SHIFT 14
130 -#define BCM2838_DMA40_DEBUG_RSTATE_BITS 4
131 -#define BCM2838_DMA40_DEBUG_WSTATE_SHIFT 18
132 -#define BCM2838_DMA40_DEBUG_WSTATE_BITS 4
133 -#define BCM2838_DMA40_DEBUG_RESET BIT(23)
134 -#define BCM2838_DMA40_DEBUG_ID_SHIFT 24
135 -#define BCM2838_DMA40_DEBUG_ID_BITS 4
136 -#define BCM2838_DMA40_DEBUG_VERSION_SHIFT 28
137 -#define BCM2838_DMA40_DEBUG_VERSION_BITS 4
138 +#define BCM2711_DMA40_DEBUG_WRITE_ERR BIT(0)
139 +#define BCM2711_DMA40_DEBUG_FIFO_ERR BIT(1)
140 +#define BCM2711_DMA40_DEBUG_READ_ERR BIT(2)
141 +#define BCM2711_DMA40_DEBUG_READ_CB_ERR BIT(3)
142 +#define BCM2711_DMA40_DEBUG_IN_ON_ERR BIT(8)
143 +#define BCM2711_DMA40_DEBUG_ABORT_ON_ERR BIT(9)
144 +#define BCM2711_DMA40_DEBUG_HALT_ON_ERR BIT(10)
145 +#define BCM2711_DMA40_DEBUG_DISABLE_CLK_GATE BIT(11)
146 +#define BCM2711_DMA40_DEBUG_RSTATE_SHIFT 14
147 +#define BCM2711_DMA40_DEBUG_RSTATE_BITS 4
148 +#define BCM2711_DMA40_DEBUG_WSTATE_SHIFT 18
149 +#define BCM2711_DMA40_DEBUG_WSTATE_BITS 4
150 +#define BCM2711_DMA40_DEBUG_RESET BIT(23)
151 +#define BCM2711_DMA40_DEBUG_ID_SHIFT 24
152 +#define BCM2711_DMA40_DEBUG_ID_BITS 4
153 +#define BCM2711_DMA40_DEBUG_VERSION_SHIFT 28
154 +#define BCM2711_DMA40_DEBUG_VERSION_BITS 4
155
156 /* Valid only for channels 0 - 3 (11 - 14) */
157 -#define BCM2838_DMA40_CHAN(n) (((n) + 11) << 8) /* Base address */
158 -#define BCM2838_DMA40_CHANIO(base, n) ((base) + BCM2838_DMA_CHAN(n))
159 +#define BCM2711_DMA40_CHAN(n) (((n) + 11) << 8) /* Base address */
160 +#define BCM2711_DMA40_CHANIO(base, n) ((base) + BCM2711_DMA_CHAN(n))
161
162 /* the max dma length for different channels */
163 #define MAX_DMA40_LEN SZ_1G
164
165 -#define BCM2838_DMA40_BURST_LEN(x) ((min(x,16) - 1) << 8)
166 -#define BCM2838_DMA40_INC BIT(12)
167 -#define BCM2838_DMA40_SIZE_32 (0 << 13)
168 -#define BCM2838_DMA40_SIZE_64 (1 << 13)
169 -#define BCM2838_DMA40_SIZE_128 (2 << 13)
170 -#define BCM2838_DMA40_SIZE_256 (3 << 13)
171 -#define BCM2838_DMA40_IGNORE BIT(15)
172 -#define BCM2838_DMA40_STRIDE(x) ((x) << 16) /* For 2D mode */
173 -
174 -#define BCM2838_DMA40_MEMCPY_FLAGS \
175 - (BCM2838_DMA40_QOS(0) | \
176 - BCM2838_DMA40_PANIC_QOS(0) | \
177 - BCM2838_DMA40_WAIT_FOR_WRITES | \
178 - BCM2838_DMA40_DISDEBUG)
179 -
180 -#define BCM2838_DMA40_MEMCPY_XFER_INFO \
181 - (BCM2838_DMA40_SIZE_128 | \
182 - BCM2838_DMA40_INC | \
183 - BCM2838_DMA40_BURST_LEN(16))
184 +#define BCM2711_DMA40_BURST_LEN(x) ((min(x,16) - 1) << 8)
185 +#define BCM2711_DMA40_INC BIT(12)
186 +#define BCM2711_DMA40_SIZE_32 (0 << 13)
187 +#define BCM2711_DMA40_SIZE_64 (1 << 13)
188 +#define BCM2711_DMA40_SIZE_128 (2 << 13)
189 +#define BCM2711_DMA40_SIZE_256 (3 << 13)
190 +#define BCM2711_DMA40_IGNORE BIT(15)
191 +#define BCM2711_DMA40_STRIDE(x) ((x) << 16) /* For 2D mode */
192 +
193 +#define BCM2711_DMA40_MEMCPY_FLAGS \
194 + (BCM2711_DMA40_QOS(0) | \
195 + BCM2711_DMA40_PANIC_QOS(0) | \
196 + BCM2711_DMA40_WAIT_FOR_WRITES | \
197 + BCM2711_DMA40_DISDEBUG)
198 +
199 +#define BCM2711_DMA40_MEMCPY_XFER_INFO \
200 + (BCM2711_DMA40_SIZE_128 | \
201 + BCM2711_DMA40_INC | \
202 + BCM2711_DMA40_BURST_LEN(16))
203
204 struct bcm2835_dmadev *memcpy_parent;
205 static void __iomem *memcpy_chan;
206 -static struct bcm2838_dma40_scb *memcpy_scb;
207 +static struct bcm2711_dma40_scb *memcpy_scb;
208 static dma_addr_t memcpy_scb_dma;
209 DEFINE_SPINLOCK(memcpy_lock);
210
211 @@ -299,7 +299,7 @@ static const struct bcm2835_dma_cfg_data
212 .chan_40bit_mask = 0,
213 };
214
215 -static const struct bcm2835_dma_cfg_data bcm2838_dma_cfg = {
216 +static const struct bcm2835_dma_cfg_data bcm2711_dma_cfg = {
217 .chan_40bit_mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
218 };
219
220 @@ -332,27 +332,27 @@ static inline struct bcm2835_desc *to_bc
221 return container_of(t, struct bcm2835_desc, vd.tx);
222 }
223
224 -static inline uint32_t to_bcm2838_ti(uint32_t info)
225 +static inline uint32_t to_bcm2711_ti(uint32_t info)
226 {
227 - return ((info & BCM2835_DMA_INT_EN) ? BCM2838_DMA40_INTEN : 0) |
228 - ((info & BCM2835_DMA_WAIT_RESP) ? BCM2838_DMA40_WAIT_RESP : 0) |
229 + return ((info & BCM2835_DMA_INT_EN) ? BCM2711_DMA40_INTEN : 0) |
230 + ((info & BCM2835_DMA_WAIT_RESP) ? BCM2711_DMA40_WAIT_RESP : 0) |
231 ((info & BCM2835_DMA_S_DREQ) ?
232 - (BCM2838_DMA40_S_DREQ | BCM2838_DMA40_WAIT_RD_RESP) : 0) |
233 - ((info & BCM2835_DMA_D_DREQ) ? BCM2838_DMA40_D_DREQ : 0) |
234 - BCM2838_DMA40_PER_MAP((info >> 16) & 0x1f);
235 + (BCM2711_DMA40_S_DREQ | BCM2711_DMA40_WAIT_RD_RESP) : 0) |
236 + ((info & BCM2835_DMA_D_DREQ) ? BCM2711_DMA40_D_DREQ : 0) |
237 + BCM2711_DMA40_PER_MAP((info >> 16) & 0x1f);
238 }
239
240 -static inline uint32_t to_bcm2838_srci(uint32_t info)
241 +static inline uint32_t to_bcm2711_srci(uint32_t info)
242 {
243 - return ((info & BCM2835_DMA_S_INC) ? BCM2838_DMA40_INC : 0);
244 + return ((info & BCM2835_DMA_S_INC) ? BCM2711_DMA40_INC : 0);
245 }
246
247 -static inline uint32_t to_bcm2838_dsti(uint32_t info)
248 +static inline uint32_t to_bcm2711_dsti(uint32_t info)
249 {
250 - return ((info & BCM2835_DMA_D_INC) ? BCM2838_DMA40_INC : 0);
251 + return ((info & BCM2835_DMA_D_INC) ? BCM2711_DMA40_INC : 0);
252 }
253
254 -static inline uint32_t to_bcm2838_cbaddr(dma_addr_t addr)
255 +static inline uint32_t to_bcm2711_cbaddr(dma_addr_t addr)
256 {
257 BUG_ON(addr & 0x1f);
258 return (addr >> 5);
259 @@ -412,12 +412,12 @@ static void bcm2835_dma_create_cb_set_le
260 }
261
262 if (c->is_40bit_channel) {
263 - struct bcm2838_dma40_scb *scb =
264 - (struct bcm2838_dma40_scb *)control_block;
265 + struct bcm2711_dma40_scb *scb =
266 + (struct bcm2711_dma40_scb *)control_block;
267
268 scb->len = cb_len;
269 /* add extrainfo bits to ti */
270 - scb->ti |= to_bcm2838_ti(finalextrainfo);
271 + scb->ti |= to_bcm2711_ti(finalextrainfo);
272 } else {
273 control_block->length = cb_len;
274 /* add extrainfo bits to info */
275 @@ -500,13 +500,13 @@ static struct bcm2835_desc *bcm2835_dma_
276 /* fill in the control block */
277 control_block = cb_entry->cb;
278 if (c->is_40bit_channel) {
279 - struct bcm2838_dma40_scb *scb =
280 - (struct bcm2838_dma40_scb *)control_block;
281 - scb->ti = to_bcm2838_ti(info);
282 + struct bcm2711_dma40_scb *scb =
283 + (struct bcm2711_dma40_scb *)control_block;
284 + scb->ti = to_bcm2711_ti(info);
285 scb->src = lower_32_bits(src);
286 - scb->srci= upper_32_bits(src) | to_bcm2838_srci(info);
287 + scb->srci= upper_32_bits(src) | to_bcm2711_srci(info);
288 scb->dst = lower_32_bits(dst);
289 - scb->dsti = upper_32_bits(dst) | to_bcm2838_dsti(info);
290 + scb->dsti = upper_32_bits(dst) | to_bcm2711_dsti(info);
291 scb->next_cb = 0;
292 } else {
293 control_block->info = info;
294 @@ -531,7 +531,7 @@ static struct bcm2835_desc *bcm2835_dma_
295 /* link this the last controlblock */
296 if (frame && c->is_40bit_channel)
297 d->cb_list[frame - 1].cb->next =
298 - to_bcm2838_cbaddr(cb_entry->paddr);
299 + to_bcm2711_cbaddr(cb_entry->paddr);
300 if (frame && !c->is_40bit_channel)
301 d->cb_list[frame - 1].cb->next = cb_entry->paddr;
302
303 @@ -547,10 +547,10 @@ static struct bcm2835_desc *bcm2835_dma_
304
305 /* the last frame requires extra flags */
306 if (c->is_40bit_channel) {
307 - struct bcm2838_dma40_scb *scb =
308 - (struct bcm2838_dma40_scb *)d->cb_list[d->frames-1].cb;
309 + struct bcm2711_dma40_scb *scb =
310 + (struct bcm2711_dma40_scb *)d->cb_list[d->frames-1].cb;
311
312 - scb->ti |= to_bcm2838_ti(finalextrainfo);
313 + scb->ti |= to_bcm2711_ti(finalextrainfo);
314 } else {
315 d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
316 }
317 @@ -581,18 +581,18 @@ static void bcm2835_dma_fill_cb_chain_wi
318 max_len = bcm2835_dma_max_frame_length(c);
319 for_each_sg(sgl, sgent, sg_len, i) {
320 if (c->is_40bit_channel) {
321 - struct bcm2838_dma40_scb *scb =
322 - (struct bcm2838_dma40_scb *)cb->cb;
323 + struct bcm2711_dma40_scb *scb =
324 + (struct bcm2711_dma40_scb *)cb->cb;
325 for (addr = sg_dma_address(sgent),
326 len = sg_dma_len(sgent);
327 len > 0;
328 addr += scb->len, len -= scb->len, scb++) {
329 if (direction == DMA_DEV_TO_MEM) {
330 scb->dst = lower_32_bits(addr);
331 - scb->dsti = upper_32_bits(addr) | BCM2838_DMA40_INC;
332 + scb->dsti = upper_32_bits(addr) | BCM2711_DMA40_INC;
333 } else {
334 scb->src = lower_32_bits(addr);
335 - scb->srci = upper_32_bits(addr) | BCM2838_DMA40_INC;
336 + scb->srci = upper_32_bits(addr) | BCM2711_DMA40_INC;
337 }
338 scb->len = min(len, max_len);
339 }
340 @@ -619,7 +619,7 @@ static void bcm2835_dma_abort(struct bcm
341 u32 wait_mask = BCM2835_DMA_WAITING_FOR_WRITES;
342
343 if (c->is_40bit_channel)
344 - wait_mask = BCM2838_DMA40_WAITING_FOR_WRITES;
345 + wait_mask = BCM2711_DMA40_WAITING_FOR_WRITES;
346
347 /*
348 * A zero control block address means the channel is idle.
349 @@ -658,10 +658,10 @@ static void bcm2835_dma_start_desc(struc
350 c->desc = d = to_bcm2835_dma_desc(&vd->tx);
351
352 if (c->is_40bit_channel) {
353 - writel(to_bcm2838_cbaddr(d->cb_list[0].paddr),
354 - c->chan_base + BCM2838_DMA40_CB);
355 - writel(BCM2838_DMA40_ACTIVE | BCM2838_DMA40_CS_FLAGS(c->dreq),
356 - c->chan_base + BCM2838_DMA40_CS);
357 + writel(to_bcm2711_cbaddr(d->cb_list[0].paddr),
358 + c->chan_base + BCM2711_DMA40_CB);
359 + writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_CS_FLAGS(c->dreq),
360 + c->chan_base + BCM2711_DMA40_CS);
361 } else {
362 writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
363 writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),
364 @@ -694,7 +694,7 @@ static irqreturn_t bcm2835_dma_callback(
365 * will remain idle despite the ACTIVE flag being set.
366 */
367 writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE |
368 - (c->is_40bit_channel ? BCM2838_DMA40_CS_FLAGS(c->dreq) :
369 + (c->is_40bit_channel ? BCM2711_DMA40_CS_FLAGS(c->dreq) :
370 BCM2835_DMA_CS_FLAGS(c->dreq)),
371 c->chan_base + BCM2835_DMA_CS);
372
373 @@ -799,14 +799,14 @@ static enum dma_status bcm2835_dma_tx_st
374 dma_addr_t pos;
375
376 if (d->dir == DMA_MEM_TO_DEV && c->is_40bit_channel)
377 - pos = readl(c->chan_base + BCM2838_DMA40_SRC) +
378 - ((readl(c->chan_base + BCM2838_DMA40_SRCI) &
379 + pos = readl(c->chan_base + BCM2711_DMA40_SRC) +
380 + ((readl(c->chan_base + BCM2711_DMA40_SRCI) &
381 0xff) << 8);
382 else if (d->dir == DMA_MEM_TO_DEV && !c->is_40bit_channel)
383 pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
384 else if (d->dir == DMA_DEV_TO_MEM && c->is_40bit_channel)
385 - pos = readl(c->chan_base + BCM2838_DMA40_DEST) +
386 - ((readl(c->chan_base + BCM2838_DMA40_DESTI) &
387 + pos = readl(c->chan_base + BCM2711_DMA40_DEST) +
388 + ((readl(c->chan_base + BCM2711_DMA40_DESTI) &
389 0xff) << 8);
390 else if (d->dir == DMA_DEV_TO_MEM && !c->is_40bit_channel)
391 pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
392 @@ -1007,7 +1007,7 @@ static struct dma_async_tx_descriptor *b
393
394 /* wrap around into a loop */
395 d->cb_list[d->frames - 1].cb->next = c->is_40bit_channel ?
396 - to_bcm2838_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr;
397 + to_bcm2711_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr;
398
399 return vchan_tx_prep(&c->vc, &d->vd, flags);
400 }
401 @@ -1095,7 +1095,7 @@ static void bcm2835_dma_free(struct bcm2
402 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
403 }
404
405 -int bcm2838_dma40_memcpy_init(void)
406 +int bcm2711_dma40_memcpy_init(void)
407 {
408 if (!memcpy_parent)
409 return -EPROBE_DEFER;
410 @@ -1108,15 +1108,15 @@ int bcm2838_dma40_memcpy_init(void)
411
412 return 0;
413 }
414 -EXPORT_SYMBOL(bcm2838_dma40_memcpy_init);
415 +EXPORT_SYMBOL(bcm2711_dma40_memcpy_init);
416
417 -void bcm2838_dma40_memcpy(dma_addr_t dst, dma_addr_t src, size_t size)
418 +void bcm2711_dma40_memcpy(dma_addr_t dst, dma_addr_t src, size_t size)
419 {
420 - struct bcm2838_dma40_scb *scb = memcpy_scb;
421 + struct bcm2711_dma40_scb *scb = memcpy_scb;
422 unsigned long flags;
423
424 if (!scb) {
425 - pr_err("bcm2838_dma40_memcpy not initialised!\n");
426 + pr_err("bcm2711_dma40_memcpy not initialised!\n");
427 return;
428 }
429
430 @@ -1124,29 +1124,29 @@ void bcm2838_dma40_memcpy(dma_addr_t dst
431
432 scb->ti = 0;
433 scb->src = lower_32_bits(src);
434 - scb->srci = upper_32_bits(src) | BCM2838_DMA40_MEMCPY_XFER_INFO;
435 + scb->srci = upper_32_bits(src) | BCM2711_DMA40_MEMCPY_XFER_INFO;
436 scb->dst = lower_32_bits(dst);
437 - scb->dsti = upper_32_bits(dst) | BCM2838_DMA40_MEMCPY_XFER_INFO;
438 + scb->dsti = upper_32_bits(dst) | BCM2711_DMA40_MEMCPY_XFER_INFO;
439 scb->len = size;
440 scb->next_cb = 0;
441
442 - writel((u32)(memcpy_scb_dma >> 5), memcpy_chan + BCM2838_DMA40_CB);
443 - writel(BCM2838_DMA40_MEMCPY_FLAGS + BCM2838_DMA40_ACTIVE,
444 - memcpy_chan + BCM2838_DMA40_CS);
445 + writel((u32)(memcpy_scb_dma >> 5), memcpy_chan + BCM2711_DMA40_CB);
446 + writel(BCM2711_DMA40_MEMCPY_FLAGS + BCM2711_DMA40_ACTIVE,
447 + memcpy_chan + BCM2711_DMA40_CS);
448
449 /* Poll for completion */
450 - while (!(readl(memcpy_chan + BCM2838_DMA40_CS) & BCM2838_DMA40_END))
451 + while (!(readl(memcpy_chan + BCM2711_DMA40_CS) & BCM2711_DMA40_END))
452 cpu_relax();
453
454 - writel(BCM2838_DMA40_END, memcpy_chan + BCM2838_DMA40_CS);
455 + writel(BCM2711_DMA40_END, memcpy_chan + BCM2711_DMA40_CS);
456
457 spin_unlock_irqrestore(&memcpy_lock, flags);
458 }
459 -EXPORT_SYMBOL(bcm2838_dma40_memcpy);
460 +EXPORT_SYMBOL(bcm2711_dma40_memcpy);
461
462 static const struct of_device_id bcm2835_dma_of_match[] = {
463 { .compatible = "brcm,bcm2835-dma", .data = &bcm2835_dma_cfg },
464 - { .compatible = "brcm,bcm2838-dma", .data = &bcm2838_dma_cfg },
465 + { .compatible = "brcm,bcm2711-dma", .data = &bcm2711_dma_cfg },
466 {},
467 };
468 MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
469 @@ -1274,9 +1274,9 @@ static int bcm2835_dma_probe(struct plat
470
471 /* And possibly one for the 40-bit DMA memcpy API */
472 if (chans_available & od->cfg_data->chan_40bit_mask &
473 - BIT(BCM2838_DMA_MEMCPY_CHAN)) {
474 + BIT(BCM2711_DMA_MEMCPY_CHAN)) {
475 memcpy_parent = od;
476 - memcpy_chan = BCM2835_DMA_CHANIO(base, BCM2838_DMA_MEMCPY_CHAN);
477 + memcpy_chan = BCM2835_DMA_CHANIO(base, BCM2711_DMA_MEMCPY_CHAN);
478 memcpy_scb = dma_alloc_coherent(memcpy_parent->ddev.dev,
479 sizeof(*memcpy_scb),
480 &memcpy_scb_dma, GFP_KERNEL);
481 @@ -1284,7 +1284,7 @@ static int bcm2835_dma_probe(struct plat
482 dev_warn(&pdev->dev,
483 "Failed to allocated memcpy scb\n");
484
485 - chans_available &= ~BIT(BCM2838_DMA_MEMCPY_CHAN);
486 + chans_available &= ~BIT(BCM2711_DMA_MEMCPY_CHAN);
487 }
488
489 /* get irqs for each channel that we support */
OpenWrt Source Repository