target/linux/bcm27xx/patches-5.15/950-0664-drm-vc4-dsi-Correct-max-divider-to-255-not-7.patch

   1 From 916c79dc5a1df708d6984f5e964eaa3de7e130f2 Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
   3 Date: Fri, 22 Oct 2021 16:48:50 +0100
   4 Subject: [PATCH] drm/vc4: dsi: Correct max divider to 255 (not 7)
   5
   6 The integer divider from parent PLL to DSI clock is capable
   7 of going up to /255, not just /7 that the driver was trying.
   8 This allows for slower link frequencies on the DSI bus where
   9 the resolution permits.
  10
  11 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_dsi.c | 2 +-
  14  1 file changed, 1 insertion(+), 1 deletion(-)
  15
  16 --- a/drivers/gpu/drm/vc4/vc4_dsi.c
  17 +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
  18 @@ -850,7 +850,7 @@ static bool vc4_dsi_encoder_mode_fixup(s
  19         /* Find what divider gets us a faster clock than the requested
  20          * pixel clock.
  21          */
  22 -       for (divider = 1; divider < 7; divider++) {
  23 +       for (divider = 1; divider < 255; divider++) {
  24                 if (parent_rate / (divider + 1) < pll_clock)
  25                         break;
  26         }