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bcm27xx: switch to kernel v6.1
[openwrt/openwrt.git] / target / linux / bcm27xx / patches-5.15 / 950-0210-media-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-int.patch
1 From 8f4208f42c896b71abe54b697cd044f0af490e67 Mon Sep 17 00:00:00 2001
2 From: Naushir Patuck <naush@raspberrypi.com>
3 Date: Wed, 1 Apr 2020 08:39:49 +0100
4 Subject: [PATCH] media: bcm2835-unicam: Driver for CCP2/CSI2 camera
5 interface
6
7 Add driver for the Unicam camera receiver block on
8 BCM283x processors.
9
10 This commit is made up of a series of changes cherry-picked from the
11 rpi-4.19.y branch.
12
13 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
14 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
15 ---
16 MAINTAINERS | 2 +-
17 drivers/media/platform/Kconfig | 1 +
18 drivers/media/platform/Makefile | 2 +
19 drivers/media/platform/bcm2835/Kconfig | 14 +
20 drivers/media/platform/bcm2835/Makefile | 3 +
21 .../media/platform/bcm2835/bcm2835-unicam.c | 2369 +++++++++++++++++
22 .../media/platform/bcm2835/vc4-regs-unicam.h | 253 ++
23 7 files changed, 2643 insertions(+), 1 deletion(-)
24 create mode 100644 drivers/media/platform/bcm2835/Kconfig
25 create mode 100644 drivers/media/platform/bcm2835/Makefile
26 create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c
27 create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h
28
29 --- a/MAINTAINERS
30 +++ b/MAINTAINERS
31 @@ -3563,7 +3563,7 @@ F: Documentation/devicetree/bindings/med
32 F: drivers/staging/media/rpivid
33
34 BROADCOM BCM2835 CAMERA DRIVER
35 -M: Dave Stevenson <dave.stevenson@raspberrypi.org>
36 +M: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
37 L: linux-media@vger.kernel.org
38 S: Maintained
39 F: drivers/media/platform/bcm2835/
40 --- a/drivers/media/platform/Kconfig
41 +++ b/drivers/media/platform/Kconfig
42 @@ -170,6 +170,7 @@ source "drivers/media/platform/am437x/Kc
43 source "drivers/media/platform/xilinx/Kconfig"
44 source "drivers/media/platform/rcar-vin/Kconfig"
45 source "drivers/media/platform/atmel/Kconfig"
46 +source "drivers/media/platform/bcm2835/Kconfig"
47 source "drivers/media/platform/sunxi/Kconfig"
48
49 config VIDEO_TI_CAL
50 --- a/drivers/media/platform/Makefile
51 +++ b/drivers/media/platform/Makefile
52 @@ -83,6 +83,8 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/
53
54 obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/
55
56 +obj-y += bcm2835/
57 +
58 obj-y += sunxi/
59
60 obj-$(CONFIG_VIDEO_MESON_GE2D) += meson/ge2d/
61 --- /dev/null
62 +++ b/drivers/media/platform/bcm2835/Kconfig
63 @@ -0,0 +1,14 @@
64 +# Broadcom VideoCore4 V4L2 camera support
65 +
66 +config VIDEO_BCM2835_UNICAM
67 + tristate "Broadcom BCM2835 Unicam video capture driver"
68 + depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER
69 + depends on ARCH_BCM2835 || COMPILE_TEST
70 + select VIDEOBUF2_DMA_CONTIG
71 + select V4L2_FWNODE
72 + help
73 + Say Y here to enable V4L2 subdevice for CSI2 receiver.
74 + This is a V4L2 subdevice that interfaces directly to the VC4 peripheral.
75 +
76 + To compile this driver as a module, choose M here. The module
77 + will be called bcm2835-unicam.
78 --- /dev/null
79 +++ b/drivers/media/platform/bcm2835/Makefile
80 @@ -0,0 +1,3 @@
81 +# Makefile for BCM2835 Unicam driver
82 +
83 +obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o
84 --- /dev/null
85 +++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c
86 @@ -0,0 +1,2369 @@
87 +// SPDX-License-Identifier: GPL-2.0-only
88 +/*
89 + * BCM2835 Unicam Capture Driver
90 + *
91 + * Copyright (C) 2017-2020 - Raspberry Pi (Trading) Ltd.
92 + *
93 + * Dave Stevenson <dave.stevenson@raspberrypi.com>
94 + *
95 + * Based on TI am437x driver by
96 + * Benoit Parrot <bparrot@ti.com>
97 + * Lad, Prabhakar <prabhakar.csengg@gmail.com>
98 + *
99 + * and TI CAL camera interface driver by
100 + * Benoit Parrot <bparrot@ti.com>
101 + *
102 + *
103 + * There are two camera drivers in the kernel for BCM283x - this one
104 + * and bcm2835-camera (currently in staging).
105 + *
106 + * This driver directly controls the Unicam peripheral - there is no
107 + * involvement with the VideoCore firmware. Unicam receives CSI-2 or
108 + * CCP2 data and writes it into SDRAM.
109 + * The only potential processing options are to repack Bayer data into an
110 + * alternate format, and applying windowing.
111 + * The repacking does not shift the data, so can repack V4L2_PIX_FMT_Sxxxx10P
112 + * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,
113 + * but not generically up to V4L2_PIX_FMT_Sxxxx16. The driver will add both
114 + * formats where the relevant formats are defined, and will automatically
115 + * configure the repacking as required.
116 + * Support for windowing may be added later.
117 + *
118 + * It should be possible to connect this driver to any sensor with a
119 + * suitable output interface and V4L2 subdevice driver.
120 + *
121 + * bcm2835-camera uses the VideoCore firmware to control the sensor,
122 + * Unicam, ISP, and all tuner control loops. Fully processed frames are
123 + * delivered to the driver by the firmware. It only has sensor drivers
124 + * for Omnivision OV5647, and Sony IMX219 sensors.
125 + *
126 + * The two drivers are mutually exclusive for the same Unicam instance.
127 + * The VideoCore firmware checks the device tree configuration during boot.
128 + * If it finds device tree nodes called csi0 or csi1 it will block the
129 + * firmware from accessing the peripheral, and bcm2835-camera will
130 + * not be able to stream data.
131 + */
132 +
133 +#include <linux/clk.h>
134 +#include <linux/delay.h>
135 +#include <linux/device.h>
136 +#include <linux/err.h>
137 +#include <linux/init.h>
138 +#include <linux/interrupt.h>
139 +#include <linux/io.h>
140 +#include <linux/module.h>
141 +#include <linux/of_device.h>
142 +#include <linux/of_graph.h>
143 +#include <linux/pinctrl/consumer.h>
144 +#include <linux/platform_device.h>
145 +#include <linux/pm_runtime.h>
146 +#include <linux/slab.h>
147 +#include <linux/uaccess.h>
148 +#include <linux/videodev2.h>
149 +
150 +#include <media/v4l2-common.h>
151 +#include <media/v4l2-ctrls.h>
152 +#include <media/v4l2-dev.h>
153 +#include <media/v4l2-device.h>
154 +#include <media/v4l2-dv-timings.h>
155 +#include <media/v4l2-event.h>
156 +#include <media/v4l2-ioctl.h>
157 +#include <media/v4l2-fwnode.h>
158 +#include <media/videobuf2-dma-contig.h>
159 +
160 +#include "vc4-regs-unicam.h"
161 +
162 +#define UNICAM_MODULE_NAME "unicam"
163 +#define UNICAM_VERSION "0.1.0"
164 +
165 +static int debug;
166 +module_param(debug, int, 0644);
167 +MODULE_PARM_DESC(debug, "Debug level 0-3");
168 +
169 +#define unicam_dbg(level, dev, fmt, arg...) \
170 + v4l2_dbg(level, debug, &(dev)->v4l2_dev, fmt, ##arg)
171 +#define unicam_info(dev, fmt, arg...) \
172 + v4l2_info(&(dev)->v4l2_dev, fmt, ##arg)
173 +#define unicam_err(dev, fmt, arg...) \
174 + v4l2_err(&(dev)->v4l2_dev, fmt, ##arg)
175 +
176 +/* To protect against a dodgy sensor driver never returning an error from
177 + * enum_mbus_code, set a maximum index value to be used.
178 + */
179 +#define MAX_ENUM_MBUS_CODE 128
180 +
181 +/*
182 + * Stride is a 16 bit register, but also has to be a multiple of 32.
183 + */
184 +#define BPL_ALIGNMENT 32
185 +#define MAX_BYTESPERLINE ((1 << 16) - BPL_ALIGNMENT)
186 +/*
187 + * Max width is therefore determined by the max stride divided by
188 + * the number of bits per pixel. Take 32bpp as a
189 + * worst case.
190 + * No imposed limit on the height, so adopt a square image for want
191 + * of anything better.
192 + */
193 +#define MAX_WIDTH (MAX_BYTESPERLINE / 4)
194 +#define MAX_HEIGHT MAX_WIDTH
195 +/* Define a nominal minimum image size */
196 +#define MIN_WIDTH 16
197 +#define MIN_HEIGHT 16
198 +
199 +/*
200 + * struct unicam_fmt - Unicam media bus format information
201 + * @pixelformat: V4L2 pixel format FCC identifier. 0 if n/a.
202 + * @repacked_fourcc: V4L2 pixel format FCC identifier if the data is expanded
203 + * out to 16bpp. 0 if n/a.
204 + * @code: V4L2 media bus format code.
205 + * @depth: Bits per pixel as delivered from the source.
206 + * @csi_dt: CSI data type.
207 + * @check_variants: Flag to denote that there are multiple mediabus formats
208 + * still in the list that could match this V4L2 format.
209 + */
210 +struct unicam_fmt {
211 + u32 fourcc;
212 + u32 repacked_fourcc;
213 + u32 code;
214 + u8 depth;
215 + u8 csi_dt;
216 + u8 check_variants;
217 +};
218 +
219 +static const struct unicam_fmt formats[] = {
220 + /* YUV Formats */
221 + {
222 + .fourcc = V4L2_PIX_FMT_YUYV,
223 + .code = MEDIA_BUS_FMT_YUYV8_2X8,
224 + .depth = 16,
225 + .csi_dt = 0x1e,
226 + .check_variants = 1,
227 + }, {
228 + .fourcc = V4L2_PIX_FMT_UYVY,
229 + .code = MEDIA_BUS_FMT_UYVY8_2X8,
230 + .depth = 16,
231 + .csi_dt = 0x1e,
232 + .check_variants = 1,
233 + }, {
234 + .fourcc = V4L2_PIX_FMT_YVYU,
235 + .code = MEDIA_BUS_FMT_YVYU8_2X8,
236 + .depth = 16,
237 + .csi_dt = 0x1e,
238 + .check_variants = 1,
239 + }, {
240 + .fourcc = V4L2_PIX_FMT_VYUY,
241 + .code = MEDIA_BUS_FMT_VYUY8_2X8,
242 + .depth = 16,
243 + .csi_dt = 0x1e,
244 + .check_variants = 1,
245 + }, {
246 + .fourcc = V4L2_PIX_FMT_YUYV,
247 + .code = MEDIA_BUS_FMT_YUYV8_1X16,
248 + .depth = 16,
249 + .csi_dt = 0x1e,
250 + }, {
251 + .fourcc = V4L2_PIX_FMT_UYVY,
252 + .code = MEDIA_BUS_FMT_UYVY8_1X16,
253 + .depth = 16,
254 + .csi_dt = 0x1e,
255 + }, {
256 + .fourcc = V4L2_PIX_FMT_YVYU,
257 + .code = MEDIA_BUS_FMT_YVYU8_1X16,
258 + .depth = 16,
259 + .csi_dt = 0x1e,
260 + }, {
261 + .fourcc = V4L2_PIX_FMT_VYUY,
262 + .code = MEDIA_BUS_FMT_VYUY8_1X16,
263 + .depth = 16,
264 + .csi_dt = 0x1e,
265 + }, {
266 + /* RGB Formats */
267 + .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
268 + .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
269 + .depth = 16,
270 + .csi_dt = 0x22,
271 + }, {
272 + .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
273 + .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
274 + .depth = 16,
275 + .csi_dt = 0x22
276 + }, {
277 + .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
278 + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
279 + .depth = 16,
280 + .csi_dt = 0x21,
281 + }, {
282 + .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
283 + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
284 + .depth = 16,
285 + .csi_dt = 0x21,
286 + }, {
287 + .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */
288 + .code = MEDIA_BUS_FMT_RGB888_1X24,
289 + .depth = 24,
290 + .csi_dt = 0x24,
291 + }, {
292 + .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
293 + .code = MEDIA_BUS_FMT_BGR888_1X24,
294 + .depth = 24,
295 + .csi_dt = 0x24,
296 + }, {
297 + .fourcc = V4L2_PIX_FMT_RGB32, /* argb */
298 + .code = MEDIA_BUS_FMT_ARGB8888_1X32,
299 + .depth = 32,
300 + .csi_dt = 0x0,
301 + }, {
302 + /* Bayer Formats */
303 + .fourcc = V4L2_PIX_FMT_SBGGR8,
304 + .code = MEDIA_BUS_FMT_SBGGR8_1X8,
305 + .depth = 8,
306 + .csi_dt = 0x2a,
307 + }, {
308 + .fourcc = V4L2_PIX_FMT_SGBRG8,
309 + .code = MEDIA_BUS_FMT_SGBRG8_1X8,
310 + .depth = 8,
311 + .csi_dt = 0x2a,
312 + }, {
313 + .fourcc = V4L2_PIX_FMT_SGRBG8,
314 + .code = MEDIA_BUS_FMT_SGRBG8_1X8,
315 + .depth = 8,
316 + .csi_dt = 0x2a,
317 + }, {
318 + .fourcc = V4L2_PIX_FMT_SRGGB8,
319 + .code = MEDIA_BUS_FMT_SRGGB8_1X8,
320 + .depth = 8,
321 + .csi_dt = 0x2a,
322 + }, {
323 + .fourcc = V4L2_PIX_FMT_SBGGR10P,
324 + .repacked_fourcc = V4L2_PIX_FMT_SBGGR10,
325 + .code = MEDIA_BUS_FMT_SBGGR10_1X10,
326 + .depth = 10,
327 + .csi_dt = 0x2b,
328 + }, {
329 + .fourcc = V4L2_PIX_FMT_SGBRG10P,
330 + .repacked_fourcc = V4L2_PIX_FMT_SGBRG10,
331 + .code = MEDIA_BUS_FMT_SGBRG10_1X10,
332 + .depth = 10,
333 + .csi_dt = 0x2b,
334 + }, {
335 + .fourcc = V4L2_PIX_FMT_SGRBG10P,
336 + .repacked_fourcc = V4L2_PIX_FMT_SGRBG10,
337 + .code = MEDIA_BUS_FMT_SGRBG10_1X10,
338 + .depth = 10,
339 + .csi_dt = 0x2b,
340 + }, {
341 + .fourcc = V4L2_PIX_FMT_SRGGB10P,
342 + .repacked_fourcc = V4L2_PIX_FMT_SRGGB10,
343 + .code = MEDIA_BUS_FMT_SRGGB10_1X10,
344 + .depth = 10,
345 + .csi_dt = 0x2b,
346 + }, {
347 + .fourcc = V4L2_PIX_FMT_SBGGR12P,
348 + .repacked_fourcc = V4L2_PIX_FMT_SBGGR12,
349 + .code = MEDIA_BUS_FMT_SBGGR12_1X12,
350 + .depth = 12,
351 + .csi_dt = 0x2c,
352 + }, {
353 + .fourcc = V4L2_PIX_FMT_SGBRG12P,
354 + .repacked_fourcc = V4L2_PIX_FMT_SGBRG12,
355 + .code = MEDIA_BUS_FMT_SGBRG12_1X12,
356 + .depth = 12,
357 + .csi_dt = 0x2c,
358 + }, {
359 + .fourcc = V4L2_PIX_FMT_SGRBG12P,
360 + .repacked_fourcc = V4L2_PIX_FMT_SGRBG12,
361 + .code = MEDIA_BUS_FMT_SGRBG12_1X12,
362 + .depth = 12,
363 + .csi_dt = 0x2c,
364 + }, {
365 + .fourcc = V4L2_PIX_FMT_SRGGB12P,
366 + .repacked_fourcc = V4L2_PIX_FMT_SRGGB12,
367 + .code = MEDIA_BUS_FMT_SRGGB12_1X12,
368 + .depth = 12,
369 + .csi_dt = 0x2c,
370 + }, {
371 + .fourcc = V4L2_PIX_FMT_SBGGR14P,
372 + .code = MEDIA_BUS_FMT_SBGGR14_1X14,
373 + .depth = 14,
374 + .csi_dt = 0x2d,
375 + }, {
376 + .fourcc = V4L2_PIX_FMT_SGBRG14P,
377 + .code = MEDIA_BUS_FMT_SGBRG14_1X14,
378 + .depth = 14,
379 + .csi_dt = 0x2d,
380 + }, {
381 + .fourcc = V4L2_PIX_FMT_SGRBG14P,
382 + .code = MEDIA_BUS_FMT_SGRBG14_1X14,
383 + .depth = 14,
384 + .csi_dt = 0x2d,
385 + }, {
386 + .fourcc = V4L2_PIX_FMT_SRGGB14P,
387 + .code = MEDIA_BUS_FMT_SRGGB14_1X14,
388 + .depth = 14,
389 + .csi_dt = 0x2d,
390 + }, {
391 + /*
392 + * 16 bit Bayer formats could be supported, but there is no CSI2
393 + * data_type defined for raw 16, and no sensors that produce it at
394 + * present.
395 + */
396 +
397 + /* Greyscale formats */
398 + .fourcc = V4L2_PIX_FMT_GREY,
399 + .code = MEDIA_BUS_FMT_Y8_1X8,
400 + .depth = 8,
401 + .csi_dt = 0x2a,
402 + }, {
403 + .fourcc = V4L2_PIX_FMT_Y10P,
404 + .repacked_fourcc = V4L2_PIX_FMT_Y10,
405 + .code = MEDIA_BUS_FMT_Y10_1X10,
406 + .depth = 10,
407 + .csi_dt = 0x2b,
408 + }, {
409 + /* NB There is no packed V4L2 fourcc for this format. */
410 + .repacked_fourcc = V4L2_PIX_FMT_Y12,
411 + .code = MEDIA_BUS_FMT_Y12_1X12,
412 + .depth = 12,
413 + .csi_dt = 0x2c,
414 + },
415 +};
416 +
417 +struct unicam_dmaqueue {
418 + struct list_head active;
419 +};
420 +
421 +struct unicam_buffer {
422 + struct vb2_v4l2_buffer vb;
423 + struct list_head list;
424 +};
425 +
426 +struct unicam_cfg {
427 + /* peripheral base address */
428 + void __iomem *base;
429 + /* clock gating base address */
430 + void __iomem *clk_gate_base;
431 +};
432 +
433 +#define MAX_POSSIBLE_PIX_FMTS (ARRAY_SIZE(formats))
434 +
435 +struct unicam_device {
436 + /* V4l2 specific parameters */
437 + /* Identifies video device for this channel */
438 + struct video_device video_dev;
439 + struct v4l2_ctrl_handler ctrl_handler;
440 +
441 + struct v4l2_fwnode_endpoint endpoint;
442 +
443 + struct v4l2_async_subdev asd;
444 +
445 + /* unicam cfg */
446 + struct unicam_cfg cfg;
447 + /* clock handle */
448 + struct clk *clock;
449 + /* V4l2 device */
450 + struct v4l2_device v4l2_dev;
451 + struct media_device mdev;
452 + struct media_pad pad;
453 +
454 + /* parent device */
455 + struct platform_device *pdev;
456 + /* subdevice async Notifier */
457 + struct v4l2_async_notifier notifier;
458 + unsigned int sequence;
459 +
460 + /* ptr to sub device */
461 + struct v4l2_subdev *sensor;
462 + /* Pad config for the sensor */
463 + struct v4l2_subdev_pad_config *sensor_config;
464 + /* current input at the sub device */
465 + int current_input;
466 +
467 + /* Pointer pointing to current v4l2_buffer */
468 + struct unicam_buffer *cur_frm;
469 + /* Pointer pointing to next v4l2_buffer */
470 + struct unicam_buffer *next_frm;
471 +
472 + /* video capture */
473 + const struct unicam_fmt *fmt;
474 + /* Used to store current pixel format */
475 + struct v4l2_format v_fmt;
476 + /* Used to store current mbus frame format */
477 + struct v4l2_mbus_framefmt m_fmt;
478 +
479 + unsigned int virtual_channel;
480 + enum v4l2_mbus_type bus_type;
481 + /*
482 + * Stores bus.mipi_csi2.flags for CSI2 sensors, or
483 + * bus.mipi_csi1.strobe for CCP2.
484 + */
485 + unsigned int bus_flags;
486 + unsigned int max_data_lanes;
487 + unsigned int active_data_lanes;
488 +
489 + struct v4l2_rect crop;
490 +
491 + /* Currently selected input on subdev */
492 + int input;
493 +
494 + /* Buffer queue used in video-buf */
495 + struct vb2_queue buffer_queue;
496 + /* Queue of filled frames */
497 + struct unicam_dmaqueue dma_queue;
498 + /* IRQ lock for DMA queue */
499 + spinlock_t dma_queue_lock;
500 + /* lock used to access this structure */
501 + struct mutex lock;
502 + /* Flag to denote that we are processing buffers */
503 + int streaming;
504 +};
505 +
506 +/* Hardware access */
507 +#define clk_write(dev, val) writel((val) | 0x5a000000, (dev)->clk_gate_base)
508 +#define clk_read(dev) readl((dev)->clk_gate_base)
509 +
510 +#define reg_read(dev, offset) readl((dev)->base + (offset))
511 +#define reg_write(dev, offset, val) writel(val, (dev)->base + (offset))
512 +
513 +#define reg_read_field(dev, offset, mask) get_field(reg_read((dev), (offset), \
514 + mask))
515 +
516 +static inline int get_field(u32 value, u32 mask)
517 +{
518 + return (value & mask) >> __ffs(mask);
519 +}
520 +
521 +static inline void set_field(u32 *valp, u32 field, u32 mask)
522 +{
523 + u32 val = *valp;
524 +
525 + val &= ~mask;
526 + val |= (field << __ffs(mask)) & mask;
527 + *valp = val;
528 +}
529 +
530 +static inline void reg_write_field(struct unicam_cfg *dev, u32 offset,
531 + u32 field, u32 mask)
532 +{
533 + u32 val = reg_read((dev), (offset));
534 +
535 + set_field(&val, field, mask);
536 + reg_write((dev), (offset), val);
537 +}
538 +
539 +/* Power management functions */
540 +static inline int unicam_runtime_get(struct unicam_device *dev)
541 +{
542 + return pm_runtime_get_sync(&dev->pdev->dev);
543 +}
544 +
545 +static inline void unicam_runtime_put(struct unicam_device *dev)
546 +{
547 + pm_runtime_put_sync(&dev->pdev->dev);
548 +}
549 +
550 +/* Format setup functions */
551 +static const struct unicam_fmt *find_format_by_code(u32 code)
552 +{
553 + unsigned int i;
554 +
555 + for (i = 0; i < ARRAY_SIZE(formats); i++) {
556 + if (formats[i].code == code)
557 + return &formats[i];
558 + }
559 +
560 + return NULL;
561 +}
562 +
563 +static int check_mbus_format(struct unicam_device *dev,
564 + const struct unicam_fmt *format)
565 +{
566 + struct v4l2_subdev_mbus_code_enum mbus_code;
567 + int ret = 0;
568 + int i;
569 +
570 + for (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {
571 + memset(&mbus_code, 0, sizeof(mbus_code));
572 + mbus_code.index = i;
573 + mbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;
574 +
575 + ret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,
576 + NULL, &mbus_code);
577 +
578 + if (!ret && mbus_code.code == format->code)
579 + return 1;
580 + }
581 +
582 + return 0;
583 +}
584 +
585 +static const struct unicam_fmt *find_format_by_pix(struct unicam_device *dev,
586 + u32 pixelformat)
587 +{
588 + unsigned int i;
589 +
590 + for (i = 0; i < ARRAY_SIZE(formats); i++) {
591 + if (formats[i].fourcc == pixelformat ||
592 + formats[i].repacked_fourcc == pixelformat) {
593 + if (formats[i].check_variants &&
594 + !check_mbus_format(dev, &formats[i]))
595 + continue;
596 + return &formats[i];
597 + }
598 + }
599 +
600 + return NULL;
601 +}
602 +
603 +static inline unsigned int bytes_per_line(u32 width,
604 + const struct unicam_fmt *fmt,
605 + u32 v4l2_fourcc)
606 +{
607 + if (v4l2_fourcc == fmt->repacked_fourcc)
608 + /* Repacking always goes to 16bpp */
609 + return ALIGN(width << 1, BPL_ALIGNMENT);
610 + else
611 + return ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);
612 +}
613 +
614 +static int __subdev_get_format(struct unicam_device *dev,
615 + struct v4l2_mbus_framefmt *fmt)
616 +{
617 + struct v4l2_subdev_format sd_fmt = {
618 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
619 + };
620 + int ret;
621 +
622 + ret = v4l2_subdev_call(dev->sensor, pad, get_fmt, dev->sensor_config,
623 + &sd_fmt);
624 + if (ret < 0)
625 + return ret;
626 +
627 + *fmt = sd_fmt.format;
628 +
629 + unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__,
630 + fmt->width, fmt->height, fmt->code);
631 +
632 + return 0;
633 +}
634 +
635 +static int __subdev_set_format(struct unicam_device *dev,
636 + struct v4l2_mbus_framefmt *fmt)
637 +{
638 + struct v4l2_subdev_format sd_fmt = {
639 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
640 + };
641 + int ret;
642 +
643 + sd_fmt.format = *fmt;
644 +
645 + ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
646 + &sd_fmt);
647 + if (ret < 0)
648 + return ret;
649 +
650 + unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__,
651 + fmt->width, fmt->height, fmt->code);
652 +
653 + return 0;
654 +}
655 +
656 +static int unicam_calc_format_size_bpl(struct unicam_device *dev,
657 + const struct unicam_fmt *fmt,
658 + struct v4l2_format *f)
659 +{
660 + unsigned int min_bytesperline;
661 +
662 + v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,
663 + &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,
664 + 0);
665 +
666 + min_bytesperline = bytes_per_line(f->fmt.pix.width, fmt,
667 + f->fmt.pix.pixelformat);
668 +
669 + if (f->fmt.pix.bytesperline > min_bytesperline &&
670 + f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)
671 + f->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,
672 + BPL_ALIGNMENT);
673 + else
674 + f->fmt.pix.bytesperline = min_bytesperline;
675 +
676 + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
677 +
678 + unicam_dbg(3, dev, "%s: fourcc: %08X size: %dx%d bpl:%d img_size:%d\n",
679 + __func__,
680 + f->fmt.pix.pixelformat,
681 + f->fmt.pix.width, f->fmt.pix.height,
682 + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
683 +
684 + return 0;
685 +}
686 +
687 +static int unicam_reset_format(struct unicam_device *dev)
688 +{
689 + struct v4l2_mbus_framefmt mbus_fmt;
690 + int ret;
691 +
692 + ret = __subdev_get_format(dev, &mbus_fmt);
693 + if (ret) {
694 + unicam_err(dev, "Failed to get_format - ret %d\n", ret);
695 + return ret;
696 + }
697 +
698 + if (mbus_fmt.code != dev->fmt->code) {
699 + unicam_err(dev, "code mismatch - fmt->code %08x, mbus_fmt.code %08x\n",
700 + dev->fmt->code, mbus_fmt.code);
701 + return ret;
702 + }
703 +
704 + v4l2_fill_pix_format(&dev->v_fmt.fmt.pix, &mbus_fmt);
705 + dev->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
706 +
707 + unicam_calc_format_size_bpl(dev, dev->fmt, &dev->v_fmt);
708 +
709 + dev->m_fmt = mbus_fmt;
710 +
711 + return 0;
712 +}
713 +
714 +static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr)
715 +{
716 + /*
717 + * dmaaddr should be a 32-bit address with the top two bits set to 0x3
718 + * to signify uncached access through the Videocore memory controller.
719 + */
720 + BUG_ON((dmaaddr >> 30) != 0x3);
721 +
722 + reg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);
723 + reg_write(&dev->cfg, UNICAM_IBEA0,
724 + dmaaddr + dev->v_fmt.fmt.pix.sizeimage);
725 +}
726 +
727 +static inline unsigned int unicam_get_lines_done(struct unicam_device *dev)
728 +{
729 + dma_addr_t start_addr, cur_addr;
730 + unsigned int stride = dev->v_fmt.fmt.pix.bytesperline;
731 + struct unicam_buffer *frm = dev->cur_frm;
732 +
733 + if (!frm)
734 + return 0;
735 +
736 + start_addr = vb2_dma_contig_plane_dma_addr(&frm->vb.vb2_buf, 0);
737 + cur_addr = reg_read(&dev->cfg, UNICAM_IBWP);
738 + return (unsigned int)(cur_addr - start_addr) / stride;
739 +}
740 +
741 +static inline void unicam_schedule_next_buffer(struct unicam_device *dev)
742 +{
743 + struct unicam_dmaqueue *dma_q = &dev->dma_queue;
744 + struct unicam_buffer *buf;
745 + dma_addr_t addr;
746 +
747 + buf = list_entry(dma_q->active.next, struct unicam_buffer, list);
748 + dev->next_frm = buf;
749 + list_del(&buf->list);
750 +
751 + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
752 + unicam_wr_dma_addr(dev, addr);
753 +}
754 +
755 +static inline void unicam_process_buffer_complete(struct unicam_device *dev)
756 +{
757 + dev->cur_frm->vb.field = dev->m_fmt.field;
758 + dev->cur_frm->vb.sequence = dev->sequence++;
759 +
760 + vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
761 + dev->cur_frm = dev->next_frm;
762 +}
763 +
764 +/*
765 + * unicam_isr : ISR handler for unicam capture
766 + * @irq: irq number
767 + * @dev_id: dev_id ptr
768 + *
769 + * It changes status of the captured buffer, takes next buffer from the queue
770 + * and sets its address in unicam registers
771 + */
772 +static irqreturn_t unicam_isr(int irq, void *dev)
773 +{
774 + struct unicam_device *unicam = (struct unicam_device *)dev;
775 + struct unicam_cfg *cfg = &unicam->cfg;
776 + struct unicam_dmaqueue *dma_q = &unicam->dma_queue;
777 + unsigned int lines_done = unicam_get_lines_done(dev);
778 + unsigned int sequence = unicam->sequence;
779 + int ista, sta;
780 +
781 + /*
782 + * Don't service interrupts if not streaming.
783 + * Avoids issues if the VPU should enable the
784 + * peripheral without the kernel knowing (that
785 + * shouldn't happen, but causes issues if it does).
786 + */
787 + if (!unicam->streaming)
788 + return IRQ_HANDLED;
789 +
790 + sta = reg_read(cfg, UNICAM_STA);
791 + /* Write value back to clear the interrupts */
792 + reg_write(cfg, UNICAM_STA, sta);
793 +
794 + ista = reg_read(cfg, UNICAM_ISTA);
795 + /* Write value back to clear the interrupts */
796 + reg_write(cfg, UNICAM_ISTA, ista);
797 +
798 + unicam_dbg(3, unicam, "ISR: ISTA: 0x%X, STA: 0x%X, sequence %d, lines done %d",
799 + ista, sta, sequence, lines_done);
800 +
801 + if (!(sta && (UNICAM_IS | UNICAM_PI0)))
802 + return IRQ_HANDLED;
803 +
804 + if (ista & UNICAM_FSI) {
805 + /*
806 + * Timestamp is to be when the first data byte was captured,
807 + * aka frame start.
808 + */
809 + if (unicam->cur_frm)
810 + unicam->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
811 + }
812 + if (ista & UNICAM_FEI || sta & UNICAM_PI0) {
813 + /*
814 + * Ensure we have swapped buffers already as we can't
815 + * stop the peripheral. Overwrite the frame we've just
816 + * captured instead.
817 + */
818 + if (unicam->cur_frm && unicam->cur_frm != unicam->next_frm)
819 + unicam_process_buffer_complete(unicam);
820 + }
821 +
822 + /* Cannot swap buffer at frame end, there may be a race condition
823 + * where the HW does not actually swap it if the new frame has
824 + * already started.
825 + */
826 + if (ista & (UNICAM_FSI | UNICAM_LCI) && !(ista & UNICAM_FEI)) {
827 + spin_lock(&unicam->dma_queue_lock);
828 + if (!list_empty(&dma_q->active) &&
829 + unicam->cur_frm == unicam->next_frm)
830 + unicam_schedule_next_buffer(unicam);
831 + spin_unlock(&unicam->dma_queue_lock);
832 + }
833 +
834 + if (reg_read(&unicam->cfg, UNICAM_ICTL) & UNICAM_FCM) {
835 + /* Switch out of trigger mode if selected */
836 + reg_write_field(&unicam->cfg, UNICAM_ICTL, 1, UNICAM_TFC);
837 + reg_write_field(&unicam->cfg, UNICAM_ICTL, 0, UNICAM_FCM);
838 + }
839 + return IRQ_HANDLED;
840 +}
841 +
842 +static int unicam_querycap(struct file *file, void *priv,
843 + struct v4l2_capability *cap)
844 +{
845 + struct unicam_device *dev = video_drvdata(file);
846 +
847 + strlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));
848 + strlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));
849 +
850 + snprintf(cap->bus_info, sizeof(cap->bus_info),
851 + "platform:%s", dev->v4l2_dev.name);
852 +
853 + return 0;
854 +}
855 +
856 +static int unicam_enum_fmt_vid_cap(struct file *file, void *priv,
857 + struct v4l2_fmtdesc *f)
858 +{
859 + struct unicam_device *dev = video_drvdata(file);
860 + struct v4l2_subdev_mbus_code_enum mbus_code;
861 + const struct unicam_fmt *fmt = NULL;
862 + int index = 0;
863 + int ret = 0;
864 + int i;
865 +
866 + for (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {
867 + memset(&mbus_code, 0, sizeof(mbus_code));
868 + mbus_code.index = i;
869 +
870 + ret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,
871 + NULL, &mbus_code);
872 + if (ret < 0) {
873 + unicam_dbg(2, dev,
874 + "subdev->enum_mbus_code idx %d returned %d - index invalid\n",
875 + i, ret);
876 + return -EINVAL;
877 + }
878 +
879 + fmt = find_format_by_code(mbus_code.code);
880 + if (fmt) {
881 + if (fmt->fourcc) {
882 + if (index == f->index) {
883 + f->pixelformat = fmt->fourcc;
884 + break;
885 + }
886 + index++;
887 + }
888 + if (fmt->repacked_fourcc) {
889 + if (index == f->index) {
890 + f->pixelformat = fmt->repacked_fourcc;
891 + break;
892 + }
893 + index++;
894 + }
895 + }
896 + }
897 +
898 + return 0;
899 +}
900 +
901 +static int unicam_g_fmt_vid_cap(struct file *file, void *priv,
902 + struct v4l2_format *f)
903 +{
904 + struct unicam_device *dev = video_drvdata(file);
905 +
906 + *f = dev->v_fmt;
907 +
908 + return 0;
909 +}
910 +
911 +static
912 +const struct unicam_fmt *get_first_supported_format(struct unicam_device *dev)
913 +{
914 + struct v4l2_subdev_mbus_code_enum mbus_code;
915 + const struct unicam_fmt *fmt = NULL;
916 + int ret;
917 + int j;
918 +
919 + for (j = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++j) {
920 + memset(&mbus_code, 0, sizeof(mbus_code));
921 + mbus_code.index = j;
922 + ret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,
923 + &mbus_code);
924 + if (ret < 0) {
925 + unicam_dbg(2, dev,
926 + "subdev->enum_mbus_code idx %d returned %d - continue\n",
927 + j, ret);
928 + continue;
929 + }
930 +
931 + unicam_dbg(2, dev, "subdev %s: code: 0x%08x idx: %d\n",
932 + dev->sensor->name, mbus_code.code, j);
933 +
934 + fmt = find_format_by_code(mbus_code.code);
935 + unicam_dbg(2, dev, "fmt 0x%08x returned as %p, V4L2 FOURCC 0x%08x, csi_dt 0x%02x\n",
936 + mbus_code.code, fmt, fmt ? fmt->fourcc : 0,
937 + fmt ? fmt->csi_dt : 0);
938 + if (fmt)
939 + return fmt;
940 + }
941 +
942 + return NULL;
943 +}
944 +
945 +static int unicam_try_fmt_vid_cap(struct file *file, void *priv,
946 + struct v4l2_format *f)
947 +{
948 + struct unicam_device *dev = video_drvdata(file);
949 + struct v4l2_subdev_format sd_fmt = {
950 + .which = V4L2_SUBDEV_FORMAT_TRY,
951 + };
952 + struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
953 + const struct unicam_fmt *fmt;
954 + int ret;
955 +
956 + fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
957 + if (!fmt) {
958 + /* Pixel format not supported by unicam. Choose the first
959 + * supported format, and let the sensor choose something else.
960 + */
961 + unicam_dbg(3, dev, "Fourcc format (0x%08x) not found. Use first format.\n",
962 + f->fmt.pix.pixelformat);
963 +
964 + fmt = &formats[0];
965 + f->fmt.pix.pixelformat = fmt->fourcc;
966 + }
967 +
968 + v4l2_fill_mbus_format(mbus_fmt, &f->fmt.pix, fmt->code);
969 + /*
970 + * No support for receiving interlaced video, so never
971 + * request it from the sensor subdev.
972 + */
973 + mbus_fmt->field = V4L2_FIELD_NONE;
974 +
975 + ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
976 + &sd_fmt);
977 + if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)
978 + return ret;
979 +
980 + if (mbus_fmt->field != V4L2_FIELD_NONE)
981 + unicam_info(dev, "Sensor trying to send interlaced video - results may be unpredictable\n");
982 +
983 + v4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);
984 + if (mbus_fmt->code != fmt->code) {
985 + /* Sensor has returned an alternate format */
986 + fmt = find_format_by_code(mbus_fmt->code);
987 + if (!fmt) {
988 + /* The alternate format is one unicam can't support.
989 + * Find the first format that is supported by both, and
990 + * then set that.
991 + */
992 + fmt = get_first_supported_format(dev);
993 + mbus_fmt->code = fmt->code;
994 +
995 + ret = v4l2_subdev_call(dev->sensor, pad, set_fmt,
996 + dev->sensor_config, &sd_fmt);
997 + if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)
998 + return ret;
999 +
1000 + if (mbus_fmt->field != V4L2_FIELD_NONE)
1001 + unicam_info(dev, "Sensor trying to send interlaced video - results may be unpredictable\n");
1002 +
1003 + v4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);
1004 +
1005 + if (mbus_fmt->code != fmt->code) {
1006 + /* We've set a format that the sensor reports
1007 + * as being supported, but it refuses to set it.
1008 + * Not much else we can do.
1009 + * Assume that the sensor driver may accept the
1010 + * format when it is set (rather than tried).
1011 + */
1012 + unicam_err(dev, "Sensor won't accept default format, and Unicam can't support sensor default\n");
1013 + }
1014 + }
1015 +
1016 + if (fmt->fourcc)
1017 + f->fmt.pix.pixelformat = fmt->fourcc;
1018 + else
1019 + f->fmt.pix.pixelformat = fmt->repacked_fourcc;
1020 + }
1021 +
1022 + return unicam_calc_format_size_bpl(dev, fmt, f);
1023 +}
1024 +
1025 +static int unicam_s_fmt_vid_cap(struct file *file, void *priv,
1026 + struct v4l2_format *f)
1027 +{
1028 + struct unicam_device *dev = video_drvdata(file);
1029 + struct vb2_queue *q = &dev->buffer_queue;
1030 + struct v4l2_mbus_framefmt mbus_fmt = {0};
1031 + const struct unicam_fmt *fmt;
1032 + int ret;
1033 +
1034 + if (vb2_is_busy(q))
1035 + return -EBUSY;
1036 +
1037 + ret = unicam_try_fmt_vid_cap(file, priv, f);
1038 + if (ret < 0)
1039 + return ret;
1040 +
1041 + fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
1042 + if (!fmt) {
1043 + /* Unknown pixel format - adopt a default.
1044 + * This shouldn't happen as try_fmt should have resolved any
1045 + * issues first.
1046 + */
1047 + fmt = get_first_supported_format(dev);
1048 + if (!fmt)
1049 + /* It shouldn't be possible to get here with no
1050 + * supported formats
1051 + */
1052 + return -EINVAL;
1053 + f->fmt.pix.pixelformat = fmt->fourcc;
1054 + return -EINVAL;
1055 + }
1056 +
1057 + v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);
1058 +
1059 + ret = __subdev_set_format(dev, &mbus_fmt);
1060 + if (ret) {
1061 + unicam_dbg(3, dev, "%s __subdev_set_format failed %d\n",
1062 + __func__, ret);
1063 + return ret;
1064 + }
1065 +
1066 + /* Just double check nothing has gone wrong */
1067 + if (mbus_fmt.code != fmt->code) {
1068 + unicam_dbg(3, dev,
1069 + "%s subdev changed format on us, this should not happen\n",
1070 + __func__);
1071 + return -EINVAL;
1072 + }
1073 +
1074 + dev->fmt = fmt;
1075 + dev->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;
1076 + dev->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;
1077 + unicam_reset_format(dev);
1078 +
1079 + unicam_dbg(3, dev, "%s %dx%d, mbus_fmt 0x%08X, V4L2 pix 0x%08X.\n",
1080 + __func__, dev->v_fmt.fmt.pix.width,
1081 + dev->v_fmt.fmt.pix.height, mbus_fmt.code,
1082 + dev->v_fmt.fmt.pix.pixelformat);
1083 +
1084 + *f = dev->v_fmt;
1085 +
1086 + return 0;
1087 +}
1088 +
1089 +static int unicam_queue_setup(struct vb2_queue *vq,
1090 + unsigned int *nbuffers,
1091 + unsigned int *nplanes,
1092 + unsigned int sizes[],
1093 + struct device *alloc_devs[])
1094 +{
1095 + struct unicam_device *dev = vb2_get_drv_priv(vq);
1096 + unsigned int size = dev->v_fmt.fmt.pix.sizeimage;
1097 +
1098 + if (vq->num_buffers + *nbuffers < 3)
1099 + *nbuffers = 3 - vq->num_buffers;
1100 +
1101 + if (*nplanes) {
1102 + if (sizes[0] < size) {
1103 + unicam_err(dev, "sizes[0] %i < size %u\n", sizes[0],
1104 + size);
1105 + return -EINVAL;
1106 + }
1107 + size = sizes[0];
1108 + }
1109 +
1110 + *nplanes = 1;
1111 + sizes[0] = size;
1112 +
1113 + return 0;
1114 +}
1115 +
1116 +static int unicam_buffer_prepare(struct vb2_buffer *vb)
1117 +{
1118 + struct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);
1119 + struct unicam_buffer *buf = container_of(vb, struct unicam_buffer,
1120 + vb.vb2_buf);
1121 + unsigned long size;
1122 +
1123 + if (WARN_ON(!dev->fmt))
1124 + return -EINVAL;
1125 +
1126 + size = dev->v_fmt.fmt.pix.sizeimage;
1127 + if (vb2_plane_size(vb, 0) < size) {
1128 + unicam_err(dev, "data will not fit into plane (%lu < %lu)\n",
1129 + vb2_plane_size(vb, 0), size);
1130 + return -EINVAL;
1131 + }
1132 +
1133 + vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1134 + return 0;
1135 +}
1136 +
1137 +static void unicam_buffer_queue(struct vb2_buffer *vb)
1138 +{
1139 + struct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);
1140 + struct unicam_buffer *buf = container_of(vb, struct unicam_buffer,
1141 + vb.vb2_buf);
1142 + struct unicam_dmaqueue *dma_queue = &dev->dma_queue;
1143 + unsigned long flags = 0;
1144 +
1145 + spin_lock_irqsave(&dev->dma_queue_lock, flags);
1146 + list_add_tail(&buf->list, &dma_queue->active);
1147 + spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
1148 +}
1149 +
1150 +static void unicam_set_packing_config(struct unicam_device *dev)
1151 +{
1152 + int pack, unpack;
1153 + u32 val;
1154 +
1155 + if (dev->v_fmt.fmt.pix.pixelformat == dev->fmt->fourcc) {
1156 + unpack = UNICAM_PUM_NONE;
1157 + pack = UNICAM_PPM_NONE;
1158 + } else {
1159 + switch (dev->fmt->depth) {
1160 + case 8:
1161 + unpack = UNICAM_PUM_UNPACK8;
1162 + break;
1163 + case 10:
1164 + unpack = UNICAM_PUM_UNPACK10;
1165 + break;
1166 + case 12:
1167 + unpack = UNICAM_PUM_UNPACK12;
1168 + break;
1169 + case 14:
1170 + unpack = UNICAM_PUM_UNPACK14;
1171 + break;
1172 + case 16:
1173 + unpack = UNICAM_PUM_UNPACK16;
1174 + break;
1175 + default:
1176 + unpack = UNICAM_PUM_NONE;
1177 + break;
1178 + }
1179 +
1180 + /* Repacking is always to 16bpp */
1181 + pack = UNICAM_PPM_PACK16;
1182 + }
1183 +
1184 + val = 0;
1185 + set_field(&val, unpack, UNICAM_PUM_MASK);
1186 + set_field(&val, pack, UNICAM_PPM_MASK);
1187 + reg_write(&dev->cfg, UNICAM_IPIPE, val);
1188 +}
1189 +
1190 +static void unicam_cfg_image_id(struct unicam_device *dev)
1191 +{
1192 + struct unicam_cfg *cfg = &dev->cfg;
1193 +
1194 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
1195 + /* CSI2 mode */
1196 + reg_write(cfg, UNICAM_IDI0,
1197 + (dev->virtual_channel << 6) | dev->fmt->csi_dt);
1198 + } else {
1199 + /* CCP2 mode */
1200 + reg_write(cfg, UNICAM_IDI0, (0x80 | dev->fmt->csi_dt));
1201 + }
1202 +}
1203 +
1204 +static void unicam_start_rx(struct unicam_device *dev, unsigned long addr)
1205 +{
1206 + struct unicam_cfg *cfg = &dev->cfg;
1207 + int line_int_freq = dev->v_fmt.fmt.pix.height >> 2;
1208 + unsigned int i;
1209 + u32 val;
1210 +
1211 + if (line_int_freq < 128)
1212 + line_int_freq = 128;
1213 +
1214 + /* Enable lane clocks */
1215 + val = 1;
1216 + for (i = 0; i < dev->active_data_lanes; i++)
1217 + val = val << 2 | 1;
1218 + clk_write(cfg, val);
1219 +
1220 + /* Basic init */
1221 + reg_write(cfg, UNICAM_CTRL, UNICAM_MEM);
1222 +
1223 + /* Enable analogue control, and leave in reset. */
1224 + val = UNICAM_AR;
1225 + set_field(&val, 7, UNICAM_CTATADJ_MASK);
1226 + set_field(&val, 7, UNICAM_PTATADJ_MASK);
1227 + reg_write(cfg, UNICAM_ANA, val);
1228 + usleep_range(1000, 2000);
1229 +
1230 + /* Come out of reset */
1231 + reg_write_field(cfg, UNICAM_ANA, 0, UNICAM_AR);
1232 +
1233 + /* Peripheral reset */
1234 + reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);
1235 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);
1236 +
1237 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);
1238 +
1239 + /* Enable Rx control. */
1240 + val = reg_read(cfg, UNICAM_CTRL);
1241 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
1242 + set_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);
1243 + set_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);
1244 + } else {
1245 + set_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);
1246 + set_field(&val, dev->bus_flags, UNICAM_DCM_MASK);
1247 + }
1248 + /* Packet framer timeout */
1249 + set_field(&val, 0xf, UNICAM_PFT_MASK);
1250 + set_field(&val, 128, UNICAM_OET_MASK);
1251 + reg_write(cfg, UNICAM_CTRL, val);
1252 +
1253 + reg_write(cfg, UNICAM_IHWIN, 0);
1254 + reg_write(cfg, UNICAM_IVWIN, 0);
1255 +
1256 + /* AXI bus access QoS setup */
1257 + val = reg_read(&dev->cfg, UNICAM_PRI);
1258 + set_field(&val, 0, UNICAM_BL_MASK);
1259 + set_field(&val, 0, UNICAM_BS_MASK);
1260 + set_field(&val, 0xe, UNICAM_PP_MASK);
1261 + set_field(&val, 8, UNICAM_NP_MASK);
1262 + set_field(&val, 2, UNICAM_PT_MASK);
1263 + set_field(&val, 1, UNICAM_PE);
1264 + reg_write(cfg, UNICAM_PRI, val);
1265 +
1266 + reg_write_field(cfg, UNICAM_ANA, 0, UNICAM_DDL);
1267 +
1268 + /* Always start in trigger frame capture mode (UNICAM_FCM set) */
1269 + val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM;
1270 + set_field(&val, line_int_freq, UNICAM_LCIE_MASK);
1271 + reg_write(cfg, UNICAM_ICTL, val);
1272 + reg_write(cfg, UNICAM_STA, UNICAM_STA_MASK_ALL);
1273 + reg_write(cfg, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);
1274 +
1275 + /* tclk_term_en */
1276 + reg_write_field(cfg, UNICAM_CLT, 2, UNICAM_CLT1_MASK);
1277 + /* tclk_settle */
1278 + reg_write_field(cfg, UNICAM_CLT, 6, UNICAM_CLT2_MASK);
1279 + /* td_term_en */
1280 + reg_write_field(cfg, UNICAM_DLT, 2, UNICAM_DLT1_MASK);
1281 + /* ths_settle */
1282 + reg_write_field(cfg, UNICAM_DLT, 6, UNICAM_DLT2_MASK);
1283 + /* trx_enable */
1284 + reg_write_field(cfg, UNICAM_DLT, 0, UNICAM_DLT3_MASK);
1285 +
1286 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_SOE);
1287 +
1288 + /* Packet compare setup - required to avoid missing frame ends */
1289 + val = 0;
1290 + set_field(&val, 1, UNICAM_PCE);
1291 + set_field(&val, 1, UNICAM_GI);
1292 + set_field(&val, 1, UNICAM_CPH);
1293 + set_field(&val, 0, UNICAM_PCVC_MASK);
1294 + set_field(&val, 1, UNICAM_PCDT_MASK);
1295 + reg_write(cfg, UNICAM_CMP0, val);
1296 +
1297 + /* Enable clock lane and set up terminations */
1298 + val = 0;
1299 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
1300 + /* CSI2 */
1301 + set_field(&val, 1, UNICAM_CLE);
1302 + set_field(&val, 1, UNICAM_CLLPE);
1303 + if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
1304 + set_field(&val, 1, UNICAM_CLTRE);
1305 + set_field(&val, 1, UNICAM_CLHSE);
1306 + }
1307 + } else {
1308 + /* CCP2 */
1309 + set_field(&val, 1, UNICAM_CLE);
1310 + set_field(&val, 1, UNICAM_CLHSE);
1311 + set_field(&val, 1, UNICAM_CLTRE);
1312 + }
1313 + reg_write(cfg, UNICAM_CLK, val);
1314 +
1315 + /*
1316 + * Enable required data lanes with appropriate terminations.
1317 + * The same value needs to be written to UNICAM_DATn registers for
1318 + * the active lanes, and 0 for inactive ones.
1319 + */
1320 + val = 0;
1321 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
1322 + /* CSI2 */
1323 + set_field(&val, 1, UNICAM_DLE);
1324 + set_field(&val, 1, UNICAM_DLLPE);
1325 + if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
1326 + set_field(&val, 1, UNICAM_DLTRE);
1327 + set_field(&val, 1, UNICAM_DLHSE);
1328 + }
1329 + } else {
1330 + /* CCP2 */
1331 + set_field(&val, 1, UNICAM_DLE);
1332 + set_field(&val, 1, UNICAM_DLHSE);
1333 + set_field(&val, 1, UNICAM_DLTRE);
1334 + }
1335 + reg_write(cfg, UNICAM_DAT0, val);
1336 +
1337 + if (dev->active_data_lanes == 1)
1338 + val = 0;
1339 + reg_write(cfg, UNICAM_DAT1, val);
1340 +
1341 + if (dev->max_data_lanes > 2) {
1342 + /*
1343 + * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the
1344 + * instance supports more than 2 data lanes.
1345 + */
1346 + if (dev->active_data_lanes == 2)
1347 + val = 0;
1348 + reg_write(cfg, UNICAM_DAT2, val);
1349 +
1350 + if (dev->active_data_lanes == 3)
1351 + val = 0;
1352 + reg_write(cfg, UNICAM_DAT3, val);
1353 + }
1354 +
1355 + reg_write(&dev->cfg, UNICAM_IBLS, dev->v_fmt.fmt.pix.bytesperline);
1356 + unicam_wr_dma_addr(dev, addr);
1357 + unicam_set_packing_config(dev);
1358 + unicam_cfg_image_id(dev);
1359 +
1360 + /* Disabled embedded data */
1361 + val = 0;
1362 + set_field(&val, 0, UNICAM_EDL_MASK);
1363 + reg_write(cfg, UNICAM_DCS, val);
1364 +
1365 + val = reg_read(cfg, UNICAM_MISC);
1366 + set_field(&val, 1, UNICAM_FL0);
1367 + set_field(&val, 1, UNICAM_FL1);
1368 + reg_write(cfg, UNICAM_MISC, val);
1369 +
1370 + /* Enable peripheral */
1371 + reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPE);
1372 +
1373 + /* Load image pointers */
1374 + reg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_LIP_MASK);
1375 +
1376 + /*
1377 + * Enable trigger only for the first frame to
1378 + * sync correctly to the FS from the source.
1379 + */
1380 + reg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_TFC);
1381 +}
1382 +
1383 +static void unicam_disable(struct unicam_device *dev)
1384 +{
1385 + struct unicam_cfg *cfg = &dev->cfg;
1386 +
1387 + /* Analogue lane control disable */
1388 + reg_write_field(cfg, UNICAM_ANA, 1, UNICAM_DDL);
1389 +
1390 + /* Stop the output engine */
1391 + reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_SOE);
1392 +
1393 + /* Disable the data lanes. */
1394 + reg_write(cfg, UNICAM_DAT0, 0);
1395 + reg_write(cfg, UNICAM_DAT1, 0);
1396 +
1397 + if (dev->max_data_lanes > 2) {
1398 + reg_write(cfg, UNICAM_DAT2, 0);
1399 + reg_write(cfg, UNICAM_DAT3, 0);
1400 + }
1401 +
1402 + /* Peripheral reset */
1403 + reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);
1404 + usleep_range(50, 100);
1405 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);
1406 +
1407 + /* Disable peripheral */
1408 + reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);
1409 +
1410 + /* Disable all lane clocks */
1411 + clk_write(cfg, 0);
1412 +}
1413 +
1414 +static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)
1415 +{
1416 + struct unicam_device *dev = vb2_get_drv_priv(vq);
1417 + struct unicam_dmaqueue *dma_q = &dev->dma_queue;
1418 + struct unicam_buffer *buf, *tmp;
1419 + unsigned long addr = 0;
1420 + unsigned long flags;
1421 + int ret;
1422 +
1423 + spin_lock_irqsave(&dev->dma_queue_lock, flags);
1424 + buf = list_entry(dma_q->active.next, struct unicam_buffer, list);
1425 + dev->cur_frm = buf;
1426 + dev->next_frm = buf;
1427 + list_del(&buf->list);
1428 + spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
1429 +
1430 + addr = vb2_dma_contig_plane_dma_addr(&dev->cur_frm->vb.vb2_buf, 0);
1431 + dev->sequence = 0;
1432 +
1433 + ret = unicam_runtime_get(dev);
1434 + if (ret < 0) {
1435 + unicam_dbg(3, dev, "unicam_runtime_get failed\n");
1436 + goto err_release_buffers;
1437 + }
1438 +
1439 + dev->active_data_lanes = dev->max_data_lanes;
1440 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY &&
1441 + v4l2_subdev_has_op(dev->sensor, video, g_mbus_config)) {
1442 + struct v4l2_mbus_config mbus_config;
1443 +
1444 + ret = v4l2_subdev_call(dev->sensor, video, g_mbus_config,
1445 + &mbus_config);
1446 + if (ret < 0) {
1447 + unicam_dbg(3, dev, "g_mbus_config failed\n");
1448 + goto err_pm_put;
1449 + }
1450 +
1451 + dev->active_data_lanes =
1452 + (mbus_config.flags & V4L2_MBUS_CSI2_LANE_MASK) >>
1453 + __ffs(V4L2_MBUS_CSI2_LANE_MASK);
1454 + if (!dev->active_data_lanes)
1455 + dev->active_data_lanes = dev->max_data_lanes;
1456 + }
1457 + if (dev->active_data_lanes > dev->max_data_lanes) {
1458 + unicam_err(dev, "Device has requested %u data lanes, which is >%u configured in DT\n",
1459 + dev->active_data_lanes, dev->max_data_lanes);
1460 + ret = -EINVAL;
1461 + goto err_pm_put;
1462 + }
1463 +
1464 + unicam_dbg(1, dev, "Running with %u data lanes\n",
1465 + dev->active_data_lanes);
1466 +
1467 + ret = clk_set_rate(dev->clock, 100 * 1000 * 1000);
1468 + if (ret) {
1469 + unicam_err(dev, "failed to set up clock\n");
1470 + goto err_pm_put;
1471 + }
1472 +
1473 + ret = clk_prepare_enable(dev->clock);
1474 + if (ret) {
1475 + unicam_err(dev, "Failed to enable CSI clock: %d\n", ret);
1476 + goto err_pm_put;
1477 + }
1478 + dev->streaming = 1;
1479 +
1480 + unicam_start_rx(dev, addr);
1481 +
1482 + ret = v4l2_subdev_call(dev->sensor, video, s_stream, 1);
1483 + if (ret < 0) {
1484 + unicam_err(dev, "stream on failed in subdev\n");
1485 + goto err_disable_unicam;
1486 + }
1487 +
1488 + return 0;
1489 +
1490 +err_disable_unicam:
1491 + unicam_disable(dev);
1492 + clk_disable_unprepare(dev->clock);
1493 +err_pm_put:
1494 + unicam_runtime_put(dev);
1495 +err_release_buffers:
1496 + list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1497 + list_del(&buf->list);
1498 + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1499 + }
1500 + if (dev->cur_frm != dev->next_frm)
1501 + vb2_buffer_done(&dev->next_frm->vb.vb2_buf,
1502 + VB2_BUF_STATE_QUEUED);
1503 + vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1504 + dev->next_frm = NULL;
1505 + dev->cur_frm = NULL;
1506 +
1507 + return ret;
1508 +}
1509 +
1510 +static void unicam_stop_streaming(struct vb2_queue *vq)
1511 +{
1512 + struct unicam_device *dev = vb2_get_drv_priv(vq);
1513 + struct unicam_dmaqueue *dma_q = &dev->dma_queue;
1514 + struct unicam_buffer *buf, *tmp;
1515 + unsigned long flags;
1516 +
1517 + if (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)
1518 + unicam_err(dev, "stream off failed in subdev\n");
1519 +
1520 + unicam_disable(dev);
1521 +
1522 + /* Release all active buffers */
1523 + spin_lock_irqsave(&dev->dma_queue_lock, flags);
1524 + list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1525 + list_del(&buf->list);
1526 + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1527 + }
1528 +
1529 + if (dev->cur_frm == dev->next_frm) {
1530 + vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1531 + } else {
1532 + vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1533 + vb2_buffer_done(&dev->next_frm->vb.vb2_buf,
1534 + VB2_BUF_STATE_ERROR);
1535 + }
1536 + dev->cur_frm = NULL;
1537 + dev->next_frm = NULL;
1538 + spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
1539 +
1540 + clk_disable_unprepare(dev->clock);
1541 + unicam_runtime_put(dev);
1542 +}
1543 +
1544 +static int unicam_enum_input(struct file *file, void *priv,
1545 + struct v4l2_input *inp)
1546 +{
1547 + struct unicam_device *dev = video_drvdata(file);
1548 +
1549 + if (inp->index != 0)
1550 + return -EINVAL;
1551 +
1552 + inp->type = V4L2_INPUT_TYPE_CAMERA;
1553 + if (v4l2_subdev_has_op(dev->sensor, video, s_dv_timings)) {
1554 + inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
1555 + inp->std = 0;
1556 + } else if (v4l2_subdev_has_op(dev->sensor, video, s_std)) {
1557 + inp->capabilities = V4L2_IN_CAP_STD;
1558 + if (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std)
1559 + < 0)
1560 + inp->std = V4L2_STD_ALL;
1561 + } else {
1562 + inp->capabilities = 0;
1563 + inp->std = 0;
1564 + }
1565 + sprintf(inp->name, "Camera 0");
1566 + return 0;
1567 +}
1568 +
1569 +static int unicam_g_input(struct file *file, void *priv, unsigned int *i)
1570 +{
1571 + *i = 0;
1572 +
1573 + return 0;
1574 +}
1575 +
1576 +static int unicam_s_input(struct file *file, void *priv, unsigned int i)
1577 +{
1578 + /*
1579 + * FIXME: Ideally we would like to be able to query the source
1580 + * subdevice for information over the input connectors it supports,
1581 + * and map that through in to a call to video_ops->s_routing.
1582 + * There is no infrastructure support for defining that within
1583 + * devicetree at present. Until that is implemented we can't
1584 + * map a user physical connector number to s_routing input number.
1585 + */
1586 + if (i > 0)
1587 + return -EINVAL;
1588 +
1589 + return 0;
1590 +}
1591 +
1592 +static int unicam_querystd(struct file *file, void *priv,
1593 + v4l2_std_id *std)
1594 +{
1595 + struct unicam_device *dev = video_drvdata(file);
1596 +
1597 + return v4l2_subdev_call(dev->sensor, video, querystd, std);
1598 +}
1599 +
1600 +static int unicam_g_std(struct file *file, void *priv, v4l2_std_id *std)
1601 +{
1602 + struct unicam_device *dev = video_drvdata(file);
1603 +
1604 + return v4l2_subdev_call(dev->sensor, video, g_std, std);
1605 +}
1606 +
1607 +static int unicam_s_std(struct file *file, void *priv, v4l2_std_id std)
1608 +{
1609 + struct unicam_device *dev = video_drvdata(file);
1610 + int ret;
1611 + v4l2_std_id current_std;
1612 +
1613 + ret = v4l2_subdev_call(dev->sensor, video, g_std, &current_std);
1614 + if (ret)
1615 + return ret;
1616 +
1617 + if (std == current_std)
1618 + return 0;
1619 +
1620 + if (vb2_is_busy(&dev->buffer_queue))
1621 + return -EBUSY;
1622 +
1623 + ret = v4l2_subdev_call(dev->sensor, video, s_std, std);
1624 +
1625 + /* Force recomputation of bytesperline */
1626 + dev->v_fmt.fmt.pix.bytesperline = 0;
1627 +
1628 + unicam_reset_format(dev);
1629 +
1630 + return ret;
1631 +}
1632 +
1633 +static int unicam_s_edid(struct file *file, void *priv, struct v4l2_edid *edid)
1634 +{
1635 + struct unicam_device *dev = video_drvdata(file);
1636 +
1637 + return v4l2_subdev_call(dev->sensor, pad, set_edid, edid);
1638 +}
1639 +
1640 +static int unicam_g_edid(struct file *file, void *priv, struct v4l2_edid *edid)
1641 +{
1642 + struct unicam_device *dev = video_drvdata(file);
1643 +
1644 + return v4l2_subdev_call(dev->sensor, pad, get_edid, edid);
1645 +}
1646 +
1647 +static int unicam_enum_framesizes(struct file *file, void *priv,
1648 + struct v4l2_frmsizeenum *fsize)
1649 +{
1650 + struct unicam_device *dev = video_drvdata(file);
1651 + const struct unicam_fmt *fmt;
1652 + struct v4l2_subdev_frame_size_enum fse;
1653 + int ret;
1654 +
1655 + /* check for valid format */
1656 + fmt = find_format_by_pix(dev, fsize->pixel_format);
1657 + if (!fmt) {
1658 + unicam_dbg(3, dev, "Invalid pixel code: %x\n",
1659 + fsize->pixel_format);
1660 + return -EINVAL;
1661 + }
1662 +
1663 + fse.index = fsize->index;
1664 + fse.pad = 0;
1665 + fse.code = fmt->code;
1666 +
1667 + ret = v4l2_subdev_call(dev->sensor, pad, enum_frame_size, NULL, &fse);
1668 + if (ret)
1669 + return ret;
1670 +
1671 + unicam_dbg(1, dev, "%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\n",
1672 + __func__, fse.index, fse.code, fse.min_width, fse.max_width,
1673 + fse.min_height, fse.max_height);
1674 +
1675 + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1676 + fsize->discrete.width = fse.max_width;
1677 + fsize->discrete.height = fse.max_height;
1678 +
1679 + return 0;
1680 +}
1681 +
1682 +static int unicam_enum_frameintervals(struct file *file, void *priv,
1683 + struct v4l2_frmivalenum *fival)
1684 +{
1685 + struct unicam_device *dev = video_drvdata(file);
1686 + const struct unicam_fmt *fmt;
1687 + struct v4l2_subdev_frame_interval_enum fie = {
1688 + .index = fival->index,
1689 + .width = fival->width,
1690 + .height = fival->height,
1691 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1692 + };
1693 + int ret;
1694 +
1695 + fmt = find_format_by_pix(dev, fival->pixel_format);
1696 + if (!fmt)
1697 + return -EINVAL;
1698 +
1699 + fie.code = fmt->code;
1700 + ret = v4l2_subdev_call(dev->sensor, pad, enum_frame_interval,
1701 + NULL, &fie);
1702 + if (ret)
1703 + return ret;
1704 +
1705 + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1706 + fival->discrete = fie.interval;
1707 +
1708 + return 0;
1709 +}
1710 +
1711 +static int unicam_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1712 +{
1713 + struct unicam_device *dev = video_drvdata(file);
1714 +
1715 + return v4l2_g_parm_cap(video_devdata(file), dev->sensor, a);
1716 +}
1717 +
1718 +static int unicam_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1719 +{
1720 + struct unicam_device *dev = video_drvdata(file);
1721 +
1722 + return v4l2_s_parm_cap(video_devdata(file), dev->sensor, a);
1723 +}
1724 +
1725 +static int unicam_g_dv_timings(struct file *file, void *priv,
1726 + struct v4l2_dv_timings *timings)
1727 +{
1728 + struct unicam_device *dev = video_drvdata(file);
1729 +
1730 + return v4l2_subdev_call(dev->sensor, video, g_dv_timings, timings);
1731 +}
1732 +
1733 +static int unicam_s_dv_timings(struct file *file, void *priv,
1734 + struct v4l2_dv_timings *timings)
1735 +{
1736 + struct unicam_device *dev = video_drvdata(file);
1737 + struct v4l2_dv_timings current_timings;
1738 + int ret;
1739 +
1740 + ret = v4l2_subdev_call(dev->sensor, video, g_dv_timings,
1741 + &current_timings);
1742 +
1743 + if (v4l2_match_dv_timings(timings, &current_timings, 0, false))
1744 + return 0;
1745 +
1746 + if (vb2_is_busy(&dev->buffer_queue))
1747 + return -EBUSY;
1748 +
1749 + ret = v4l2_subdev_call(dev->sensor, video, s_dv_timings, timings);
1750 +
1751 + /* Force recomputation of bytesperline */
1752 + dev->v_fmt.fmt.pix.bytesperline = 0;
1753 +
1754 + unicam_reset_format(dev);
1755 +
1756 + return ret;
1757 +}
1758 +
1759 +static int unicam_query_dv_timings(struct file *file, void *priv,
1760 + struct v4l2_dv_timings *timings)
1761 +{
1762 + struct unicam_device *dev = video_drvdata(file);
1763 +
1764 + return v4l2_subdev_call(dev->sensor, video, query_dv_timings, timings);
1765 +}
1766 +
1767 +static int unicam_enum_dv_timings(struct file *file, void *priv,
1768 + struct v4l2_enum_dv_timings *timings)
1769 +{
1770 + struct unicam_device *dev = video_drvdata(file);
1771 +
1772 + return v4l2_subdev_call(dev->sensor, pad, enum_dv_timings, timings);
1773 +}
1774 +
1775 +static int unicam_dv_timings_cap(struct file *file, void *priv,
1776 + struct v4l2_dv_timings_cap *cap)
1777 +{
1778 + struct unicam_device *dev = video_drvdata(file);
1779 +
1780 + return v4l2_subdev_call(dev->sensor, pad, dv_timings_cap, cap);
1781 +}
1782 +
1783 +static int unicam_subscribe_event(struct v4l2_fh *fh,
1784 + const struct v4l2_event_subscription *sub)
1785 +{
1786 + switch (sub->type) {
1787 + case V4L2_EVENT_SOURCE_CHANGE:
1788 + return v4l2_event_subscribe(fh, sub, 4, NULL);
1789 + }
1790 +
1791 + return v4l2_ctrl_subscribe_event(fh, sub);
1792 +}
1793 +
1794 +static int unicam_log_status(struct file *file, void *fh)
1795 +{
1796 + struct unicam_device *dev = video_drvdata(file);
1797 + struct unicam_cfg *cfg = &dev->cfg;
1798 + u32 reg;
1799 +
1800 + /* status for sub devices */
1801 + v4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);
1802 +
1803 + unicam_info(dev, "-----Receiver status-----\n");
1804 + unicam_info(dev, "V4L2 width/height: %ux%u\n",
1805 + dev->v_fmt.fmt.pix.width, dev->v_fmt.fmt.pix.height);
1806 + unicam_info(dev, "Mediabus format: %08x\n", dev->fmt->code);
1807 + unicam_info(dev, "V4L2 format: %08x\n",
1808 + dev->v_fmt.fmt.pix.pixelformat);
1809 + reg = reg_read(&dev->cfg, UNICAM_IPIPE);
1810 + unicam_info(dev, "Unpacking/packing: %u / %u\n",
1811 + get_field(reg, UNICAM_PUM_MASK),
1812 + get_field(reg, UNICAM_PPM_MASK));
1813 + unicam_info(dev, "----Live data----\n");
1814 + unicam_info(dev, "Programmed stride: %4u\n",
1815 + reg_read(cfg, UNICAM_IBLS));
1816 + unicam_info(dev, "Detected resolution: %ux%u\n",
1817 + reg_read(cfg, UNICAM_IHSTA),
1818 + reg_read(cfg, UNICAM_IVSTA));
1819 + unicam_info(dev, "Write pointer: %08x\n",
1820 + reg_read(cfg, UNICAM_IBWP));
1821 +
1822 + return 0;
1823 +}
1824 +
1825 +static void unicam_notify(struct v4l2_subdev *sd,
1826 + unsigned int notification, void *arg)
1827 +{
1828 + struct unicam_device *dev =
1829 + container_of(sd->v4l2_dev, struct unicam_device, v4l2_dev);
1830 +
1831 + switch (notification) {
1832 + case V4L2_DEVICE_NOTIFY_EVENT:
1833 + v4l2_event_queue(&dev->video_dev, arg);
1834 + break;
1835 + default:
1836 + break;
1837 + }
1838 +}
1839 +
1840 +static const struct vb2_ops unicam_video_qops = {
1841 + .wait_prepare = vb2_ops_wait_prepare,
1842 + .wait_finish = vb2_ops_wait_finish,
1843 + .queue_setup = unicam_queue_setup,
1844 + .buf_prepare = unicam_buffer_prepare,
1845 + .buf_queue = unicam_buffer_queue,
1846 + .start_streaming = unicam_start_streaming,
1847 + .stop_streaming = unicam_stop_streaming,
1848 +};
1849 +
1850 +/*
1851 + * unicam_open : This function is based on the v4l2_fh_open helper function.
1852 + * It has been augmented to handle sensor subdevice power management,
1853 + */
1854 +static int unicam_open(struct file *file)
1855 +{
1856 + struct unicam_device *dev = video_drvdata(file);
1857 + int ret;
1858 +
1859 + mutex_lock(&dev->lock);
1860 +
1861 + ret = v4l2_fh_open(file);
1862 + if (ret) {
1863 + unicam_err(dev, "v4l2_fh_open failed\n");
1864 + goto unlock;
1865 + }
1866 +
1867 + if (!v4l2_fh_is_singular_file(file))
1868 + goto unlock;
1869 +
1870 + ret = v4l2_subdev_call(dev->sensor, core, s_power, 1);
1871 + if (ret < 0 && ret != -ENOIOCTLCMD) {
1872 + v4l2_fh_release(file);
1873 + goto unlock;
1874 + }
1875 +
1876 + ret = 0;
1877 +
1878 +unlock:
1879 + mutex_unlock(&dev->lock);
1880 + return ret;
1881 +}
1882 +
1883 +static int unicam_release(struct file *file)
1884 +{
1885 + struct unicam_device *dev = video_drvdata(file);
1886 + struct v4l2_subdev *sd = dev->sensor;
1887 + bool fh_singular;
1888 + int ret;
1889 +
1890 + mutex_lock(&dev->lock);
1891 +
1892 + fh_singular = v4l2_fh_is_singular_file(file);
1893 +
1894 + ret = _vb2_fop_release(file, NULL);
1895 +
1896 + if (fh_singular)
1897 + v4l2_subdev_call(sd, core, s_power, 0);
1898 +
1899 + mutex_unlock(&dev->lock);
1900 +
1901 + return ret;
1902 +}
1903 +
1904 +/* unicam capture driver file operations */
1905 +static const struct v4l2_file_operations unicam_fops = {
1906 + .owner = THIS_MODULE,
1907 + .open = unicam_open,
1908 + .release = unicam_release,
1909 + .read = vb2_fop_read,
1910 + .poll = vb2_fop_poll,
1911 + .unlocked_ioctl = video_ioctl2,
1912 + .mmap = vb2_fop_mmap,
1913 +};
1914 +
1915 +/* unicam capture ioctl operations */
1916 +static const struct v4l2_ioctl_ops unicam_ioctl_ops = {
1917 + .vidioc_querycap = unicam_querycap,
1918 + .vidioc_enum_fmt_vid_cap = unicam_enum_fmt_vid_cap,
1919 + .vidioc_g_fmt_vid_cap = unicam_g_fmt_vid_cap,
1920 + .vidioc_s_fmt_vid_cap = unicam_s_fmt_vid_cap,
1921 + .vidioc_try_fmt_vid_cap = unicam_try_fmt_vid_cap,
1922 +
1923 + .vidioc_enum_input = unicam_enum_input,
1924 + .vidioc_g_input = unicam_g_input,
1925 + .vidioc_s_input = unicam_s_input,
1926 +
1927 + .vidioc_querystd = unicam_querystd,
1928 + .vidioc_s_std = unicam_s_std,
1929 + .vidioc_g_std = unicam_g_std,
1930 +
1931 + .vidioc_g_edid = unicam_g_edid,
1932 + .vidioc_s_edid = unicam_s_edid,
1933 +
1934 + .vidioc_enum_framesizes = unicam_enum_framesizes,
1935 + .vidioc_enum_frameintervals = unicam_enum_frameintervals,
1936 +
1937 + .vidioc_g_parm = unicam_g_parm,
1938 + .vidioc_s_parm = unicam_s_parm,
1939 +
1940 + .vidioc_s_dv_timings = unicam_s_dv_timings,
1941 + .vidioc_g_dv_timings = unicam_g_dv_timings,
1942 + .vidioc_query_dv_timings = unicam_query_dv_timings,
1943 + .vidioc_enum_dv_timings = unicam_enum_dv_timings,
1944 + .vidioc_dv_timings_cap = unicam_dv_timings_cap,
1945 +
1946 + .vidioc_reqbufs = vb2_ioctl_reqbufs,
1947 + .vidioc_create_bufs = vb2_ioctl_create_bufs,
1948 + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1949 + .vidioc_querybuf = vb2_ioctl_querybuf,
1950 + .vidioc_qbuf = vb2_ioctl_qbuf,
1951 + .vidioc_dqbuf = vb2_ioctl_dqbuf,
1952 + .vidioc_expbuf = vb2_ioctl_expbuf,
1953 + .vidioc_streamon = vb2_ioctl_streamon,
1954 + .vidioc_streamoff = vb2_ioctl_streamoff,
1955 +
1956 + .vidioc_log_status = unicam_log_status,
1957 + .vidioc_subscribe_event = unicam_subscribe_event,
1958 + .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1959 +};
1960 +
1961 +static int
1962 +unicam_async_bound(struct v4l2_async_notifier *notifier,
1963 + struct v4l2_subdev *subdev,
1964 + struct v4l2_async_subdev *asd)
1965 +{
1966 + struct unicam_device *unicam = container_of(notifier->v4l2_dev,
1967 + struct unicam_device, v4l2_dev);
1968 +
1969 + if (unicam->sensor) {
1970 + unicam_info(unicam, "Rejecting subdev %s (Already set!!)",
1971 + subdev->name);
1972 + return 0;
1973 + }
1974 +
1975 + unicam->sensor = subdev;
1976 + unicam_dbg(1, unicam, "Using sensor %s for capture\n", subdev->name);
1977 +
1978 + return 0;
1979 +}
1980 +
1981 +static int unicam_probe_complete(struct unicam_device *unicam)
1982 +{
1983 + struct video_device *vdev;
1984 + struct vb2_queue *q;
1985 + struct v4l2_mbus_framefmt mbus_fmt = {0};
1986 + const struct unicam_fmt *fmt;
1987 + int ret;
1988 +
1989 + v4l2_set_subdev_hostdata(unicam->sensor, unicam);
1990 +
1991 + unicam->v4l2_dev.notify = unicam_notify;
1992 +
1993 + unicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);
1994 + if (!unicam->sensor_config)
1995 + return -ENOMEM;
1996 +
1997 + ret = __subdev_get_format(unicam, &mbus_fmt);
1998 + if (ret) {
1999 + unicam_err(unicam, "Failed to get_format - ret %d\n", ret);
2000 + return ret;
2001 + }
2002 +
2003 + fmt = find_format_by_code(mbus_fmt.code);
2004 + if (!fmt) {
2005 + /* Find the first format that the sensor and unicam both
2006 + * support
2007 + */
2008 + fmt = get_first_supported_format(unicam);
2009 +
2010 + if (!fmt)
2011 + /* No compatible formats */
2012 + return -EINVAL;
2013 +
2014 + mbus_fmt.code = fmt->code;
2015 + ret = __subdev_set_format(unicam, &mbus_fmt);
2016 + if (ret)
2017 + return -EINVAL;
2018 + }
2019 + if (mbus_fmt.field != V4L2_FIELD_NONE) {
2020 + /* Interlaced not supported - disable it now. */
2021 + mbus_fmt.field = V4L2_FIELD_NONE;
2022 + ret = __subdev_set_format(unicam, &mbus_fmt);
2023 + if (ret)
2024 + return -EINVAL;
2025 + }
2026 +
2027 + unicam->fmt = fmt;
2028 + if (fmt->fourcc)
2029 + unicam->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
2030 + else
2031 + unicam->v_fmt.fmt.pix.pixelformat = fmt->repacked_fourcc;
2032 +
2033 + /* Read current subdev format */
2034 + unicam_reset_format(unicam);
2035 +
2036 + if (v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
2037 + v4l2_std_id tvnorms;
2038 +
2039 + if (WARN_ON(!v4l2_subdev_has_op(unicam->sensor, video,
2040 + g_tvnorms)))
2041 + /*
2042 + * Subdevice should not advertise s_std but not
2043 + * g_tvnorms
2044 + */
2045 + return -EINVAL;
2046 +
2047 + ret = v4l2_subdev_call(unicam->sensor, video,
2048 + g_tvnorms, &tvnorms);
2049 + if (WARN_ON(ret))
2050 + return -EINVAL;
2051 + unicam->video_dev.tvnorms |= tvnorms;
2052 + }
2053 +
2054 + spin_lock_init(&unicam->dma_queue_lock);
2055 + mutex_init(&unicam->lock);
2056 +
2057 + /* Add controls from the subdevice */
2058 + ret = v4l2_ctrl_add_handler(&unicam->ctrl_handler,
2059 + unicam->sensor->ctrl_handler, NULL, true);
2060 + if (ret < 0)
2061 + return ret;
2062 +
2063 + q = &unicam->buffer_queue;
2064 + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2065 + q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
2066 + q->drv_priv = unicam;
2067 + q->ops = &unicam_video_qops;
2068 + q->mem_ops = &vb2_dma_contig_memops;
2069 + q->buf_struct_size = sizeof(struct unicam_buffer);
2070 + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2071 + q->lock = &unicam->lock;
2072 + q->min_buffers_needed = 2;
2073 + q->dev = &unicam->pdev->dev;
2074 +
2075 + ret = vb2_queue_init(q);
2076 + if (ret) {
2077 + unicam_err(unicam, "vb2_queue_init() failed\n");
2078 + return ret;
2079 + }
2080 +
2081 + INIT_LIST_HEAD(&unicam->dma_queue.active);
2082 +
2083 + vdev = &unicam->video_dev;
2084 + strlcpy(vdev->name, UNICAM_MODULE_NAME, sizeof(vdev->name));
2085 + vdev->release = video_device_release_empty;
2086 + vdev->fops = &unicam_fops;
2087 + vdev->ioctl_ops = &unicam_ioctl_ops;
2088 + vdev->v4l2_dev = &unicam->v4l2_dev;
2089 + vdev->vfl_dir = VFL_DIR_RX;
2090 + vdev->queue = q;
2091 + vdev->lock = &unicam->lock;
2092 + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
2093 + V4L2_CAP_READWRITE;
2094 +
2095 + /* If the source has no controls then remove our ctrl handler. */
2096 + if (list_empty(&unicam->ctrl_handler.ctrls))
2097 + unicam->v4l2_dev.ctrl_handler = NULL;
2098 +
2099 + video_set_drvdata(vdev, unicam);
2100 + vdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;
2101 +
2102 + if (!v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
2103 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_STD);
2104 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_STD);
2105 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUMSTD);
2106 + }
2107 + if (!v4l2_subdev_has_op(unicam->sensor, video, querystd))
2108 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERYSTD);
2109 + if (!v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {
2110 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_EDID);
2111 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_EDID);
2112 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_DV_TIMINGS_CAP);
2113 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_DV_TIMINGS);
2114 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_DV_TIMINGS);
2115 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUM_DV_TIMINGS);
2116 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERY_DV_TIMINGS);
2117 + }
2118 + if (!v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_interval))
2119 + v4l2_disable_ioctl(&unicam->video_dev,
2120 + VIDIOC_ENUM_FRAMEINTERVALS);
2121 + if (!v4l2_subdev_has_op(unicam->sensor, video, g_frame_interval))
2122 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_PARM);
2123 + if (!v4l2_subdev_has_op(unicam->sensor, video, s_frame_interval))
2124 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_PARM);
2125 +
2126 + if (!v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_size))
2127 + v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUM_FRAMESIZES);
2128 +
2129 + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
2130 + if (ret) {
2131 + unicam_err(unicam, "Unable to register video device.\n");
2132 + return ret;
2133 + }
2134 +
2135 + ret = v4l2_device_register_ro_subdev_nodes(&unicam->v4l2_dev);
2136 + if (ret) {
2137 + unicam_err(unicam,
2138 + "Unable to register subdev nodes.\n");
2139 + video_unregister_device(&unicam->video_dev);
2140 + return ret;
2141 + }
2142 +
2143 + ret = media_create_pad_link(&unicam->sensor->entity, 0,
2144 + &unicam->video_dev.entity, 0,
2145 + MEDIA_LNK_FL_ENABLED |
2146 + MEDIA_LNK_FL_IMMUTABLE);
2147 + if (ret) {
2148 + unicam_err(unicam, "Unable to create pad links.\n");
2149 + video_unregister_device(&unicam->video_dev);
2150 + return ret;
2151 + }
2152 +
2153 + return 0;
2154 +}
2155 +
2156 +static int unicam_async_complete(struct v4l2_async_notifier *notifier)
2157 +{
2158 + struct unicam_device *unicam = container_of(notifier->v4l2_dev,
2159 + struct unicam_device, v4l2_dev);
2160 +
2161 + return unicam_probe_complete(unicam);
2162 +}
2163 +
2164 +static const struct v4l2_async_notifier_operations unicam_async_ops = {
2165 + .bound = unicam_async_bound,
2166 + .complete = unicam_async_complete,
2167 +};
2168 +
2169 +static int of_unicam_connect_subdevs(struct unicam_device *dev)
2170 +{
2171 + struct platform_device *pdev = dev->pdev;
2172 + struct device_node *parent, *ep_node = NULL, *remote_ep = NULL,
2173 + *sensor_node = NULL;
2174 + struct v4l2_fwnode_endpoint *ep;
2175 + struct v4l2_async_subdev *asd;
2176 + unsigned int peripheral_data_lanes;
2177 + int ret = -EINVAL;
2178 + unsigned int lane;
2179 +
2180 + parent = pdev->dev.of_node;
2181 +
2182 + asd = &dev->asd;
2183 + ep = &dev->endpoint;
2184 +
2185 + ep_node = of_graph_get_next_endpoint(parent, NULL);
2186 + if (!ep_node) {
2187 + unicam_dbg(3, dev, "can't get next endpoint\n");
2188 + goto cleanup_exit;
2189 + }
2190 +
2191 + unicam_dbg(3, dev, "ep_node is %s\n", ep_node->name);
2192 +
2193 + v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), ep);
2194 +
2195 + for (lane = 0; lane < ep->bus.mipi_csi2.num_data_lanes; lane++) {
2196 + if (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {
2197 + unicam_err(dev, "Local endpoint - data lane reordering not supported\n");
2198 + goto cleanup_exit;
2199 + }
2200 + }
2201 +
2202 + peripheral_data_lanes = ep->bus.mipi_csi2.num_data_lanes;
2203 +
2204 + sensor_node = of_graph_get_remote_port_parent(ep_node);
2205 + if (!sensor_node) {
2206 + unicam_dbg(3, dev, "can't get remote parent\n");
2207 + goto cleanup_exit;
2208 + }
2209 + unicam_dbg(3, dev, "sensor_node is %s\n", sensor_node->name);
2210 + asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2211 + asd->match.fwnode = of_fwnode_handle(sensor_node);
2212 +
2213 + remote_ep = of_graph_get_remote_endpoint(ep_node);
2214 + if (!remote_ep) {
2215 + unicam_dbg(3, dev, "can't get remote-endpoint\n");
2216 + goto cleanup_exit;
2217 + }
2218 + unicam_dbg(3, dev, "remote_ep is %s\n", remote_ep->name);
2219 + v4l2_fwnode_endpoint_parse(of_fwnode_handle(remote_ep), ep);
2220 + unicam_dbg(3, dev, "parsed remote_ep to endpoint. nr_of_link_frequencies %u, bus_type %u\n",
2221 + ep->nr_of_link_frequencies, ep->bus_type);
2222 +
2223 + switch (ep->bus_type) {
2224 + case V4L2_MBUS_CSI2_DPHY:
2225 + if (ep->bus.mipi_csi2.num_data_lanes >
2226 + peripheral_data_lanes) {
2227 + unicam_err(dev, "Subdevice %s wants too many data lanes (%u > %u)\n",
2228 + sensor_node->name,
2229 + ep->bus.mipi_csi2.num_data_lanes,
2230 + peripheral_data_lanes);
2231 + goto cleanup_exit;
2232 + }
2233 + for (lane = 0;
2234 + lane < ep->bus.mipi_csi2.num_data_lanes;
2235 + lane++) {
2236 + if (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {
2237 + unicam_err(dev, "Subdevice %s - incompatible data lane config\n",
2238 + sensor_node->name);
2239 + goto cleanup_exit;
2240 + }
2241 + }
2242 + dev->max_data_lanes = ep->bus.mipi_csi2.num_data_lanes;
2243 + dev->bus_flags = ep->bus.mipi_csi2.flags;
2244 + break;
2245 + case V4L2_MBUS_CCP2:
2246 + if (ep->bus.mipi_csi1.clock_lane != 0 ||
2247 + ep->bus.mipi_csi1.data_lane != 1) {
2248 + unicam_err(dev, "Subdevice %s incompatible lane config\n",
2249 + sensor_node->name);
2250 + goto cleanup_exit;
2251 + }
2252 + dev->max_data_lanes = 1;
2253 + dev->bus_flags = ep->bus.mipi_csi1.strobe;
2254 + break;
2255 + default:
2256 + /* Unsupported bus type */
2257 + unicam_err(dev, "sub-device %s is not a CSI2 or CCP2 device %d\n",
2258 + sensor_node->name, ep->bus_type);
2259 + goto cleanup_exit;
2260 + }
2261 +
2262 + /* Store bus type - CSI2 or CCP2 */
2263 + dev->bus_type = ep->bus_type;
2264 + unicam_dbg(3, dev, "bus_type is %d\n", dev->bus_type);
2265 +
2266 + /* Store Virtual Channel number */
2267 + dev->virtual_channel = ep->base.id;
2268 +
2269 + unicam_dbg(3, dev, "v4l2-endpoint: %s\n",
2270 + dev->bus_type == V4L2_MBUS_CSI2_DPHY ? "CSI2" : "CCP2");
2271 + unicam_dbg(3, dev, "Virtual Channel=%d\n", dev->virtual_channel);
2272 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY)
2273 + unicam_dbg(3, dev, "flags=0x%08x\n", ep->bus.mipi_csi2.flags);
2274 + unicam_dbg(3, dev, "num_data_lanes=%d\n", dev->max_data_lanes);
2275 +
2276 + unicam_dbg(1, dev, "found sub-device %s\n", sensor_node->name);
2277 +
2278 + v4l2_async_notifier_init(&dev->notifier);
2279 +
2280 + ret = v4l2_async_notifier_add_subdev(&dev->notifier, asd);
2281 + if (ret) {
2282 + unicam_err(dev, "Error adding subdevice - ret %d\n", ret);
2283 + goto cleanup_exit;
2284 + }
2285 +
2286 + dev->notifier.ops = &unicam_async_ops;
2287 + ret = v4l2_async_notifier_register(&dev->v4l2_dev,
2288 + &dev->notifier);
2289 + if (ret) {
2290 + unicam_err(dev, "Error registering async notifier - ret %d\n",
2291 + ret);
2292 + ret = -EINVAL;
2293 + }
2294 +
2295 +cleanup_exit:
2296 + if (remote_ep)
2297 + of_node_put(remote_ep);
2298 + if (sensor_node)
2299 + of_node_put(sensor_node);
2300 + if (ep_node)
2301 + of_node_put(ep_node);
2302 +
2303 + return ret;
2304 +}
2305 +
2306 +static int unicam_probe(struct platform_device *pdev)
2307 +{
2308 + struct unicam_cfg *unicam_cfg;
2309 + struct unicam_device *unicam;
2310 + struct v4l2_ctrl_handler *hdl;
2311 + struct resource *res;
2312 + int ret;
2313 +
2314 + unicam = devm_kzalloc(&pdev->dev, sizeof(*unicam), GFP_KERNEL);
2315 + if (!unicam)
2316 + return -ENOMEM;
2317 +
2318 + unicam->pdev = pdev;
2319 + unicam_cfg = &unicam->cfg;
2320 +
2321 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2322 + unicam_cfg->base = devm_ioremap_resource(&pdev->dev, res);
2323 + if (IS_ERR(unicam_cfg->base)) {
2324 + unicam_err(unicam, "Failed to get main io block\n");
2325 + return PTR_ERR(unicam_cfg->base);
2326 + }
2327 +
2328 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2329 + unicam_cfg->clk_gate_base = devm_ioremap_resource(&pdev->dev, res);
2330 + if (IS_ERR(unicam_cfg->clk_gate_base)) {
2331 + unicam_err(unicam, "Failed to get 2nd io block\n");
2332 + return PTR_ERR(unicam_cfg->clk_gate_base);
2333 + }
2334 +
2335 + unicam->clock = devm_clk_get(&pdev->dev, "lp");
2336 + if (IS_ERR(unicam->clock)) {
2337 + unicam_err(unicam, "Failed to get clock\n");
2338 + return PTR_ERR(unicam->clock);
2339 + }
2340 +
2341 + ret = platform_get_irq(pdev, 0);
2342 + if (ret <= 0) {
2343 + dev_err(&pdev->dev, "No IRQ resource\n");
2344 + return -ENODEV;
2345 + }
2346 +
2347 + ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
2348 + "unicam_capture0", unicam);
2349 + if (ret) {
2350 + dev_err(&pdev->dev, "Unable to request interrupt\n");
2351 + return -EINVAL;
2352 + }
2353 +
2354 + unicam->mdev.dev = &pdev->dev;
2355 + strscpy(unicam->mdev.model, UNICAM_MODULE_NAME,
2356 + sizeof(unicam->mdev.model));
2357 + strscpy(unicam->mdev.serial, "", sizeof(unicam->mdev.serial));
2358 + snprintf(unicam->mdev.bus_info, sizeof(unicam->mdev.bus_info),
2359 + "platform:%s %s",
2360 + pdev->dev.driver->name, dev_name(&pdev->dev));
2361 + unicam->mdev.hw_revision = 1;
2362 +
2363 + media_entity_pads_init(&unicam->video_dev.entity, 1, &unicam->pad);
2364 + media_device_init(&unicam->mdev);
2365 +
2366 + unicam->v4l2_dev.mdev = &unicam->mdev;
2367 +
2368 + ret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);
2369 + if (ret) {
2370 + unicam_err(unicam,
2371 + "Unable to register v4l2 device.\n");
2372 + goto media_cleanup;
2373 + }
2374 +
2375 + ret = media_device_register(&unicam->mdev);
2376 + if (ret < 0) {
2377 + unicam_err(unicam,
2378 + "Unable to register media-controller device.\n");
2379 + goto probe_out_v4l2_unregister;
2380 + }
2381 +
2382 + /* Reserve space for the controls */
2383 + hdl = &unicam->ctrl_handler;
2384 + ret = v4l2_ctrl_handler_init(hdl, 16);
2385 + if (ret < 0)
2386 + goto media_unregister;
2387 + unicam->v4l2_dev.ctrl_handler = hdl;
2388 +
2389 + /* set the driver data in platform device */
2390 + platform_set_drvdata(pdev, unicam);
2391 +
2392 + ret = of_unicam_connect_subdevs(unicam);
2393 + if (ret) {
2394 + dev_err(&pdev->dev, "Failed to connect subdevs\n");
2395 + goto free_hdl;
2396 + }
2397 +
2398 + /* Enable the block power domain */
2399 + pm_runtime_enable(&pdev->dev);
2400 +
2401 + return 0;
2402 +
2403 +free_hdl:
2404 + v4l2_ctrl_handler_free(hdl);
2405 +media_unregister:
2406 + media_device_unregister(&unicam->mdev);
2407 +probe_out_v4l2_unregister:
2408 + v4l2_device_unregister(&unicam->v4l2_dev);
2409 +media_cleanup:
2410 + media_device_cleanup(&unicam->mdev);
2411 +
2412 + return ret;
2413 +}
2414 +
2415 +static int unicam_remove(struct platform_device *pdev)
2416 +{
2417 + struct unicam_device *unicam = platform_get_drvdata(pdev);
2418 +
2419 + unicam_dbg(2, unicam, "%s\n", __func__);
2420 +
2421 + pm_runtime_disable(&pdev->dev);
2422 +
2423 + v4l2_async_notifier_unregister(&unicam->notifier);
2424 + v4l2_ctrl_handler_free(&unicam->ctrl_handler);
2425 + v4l2_device_unregister(&unicam->v4l2_dev);
2426 + video_unregister_device(&unicam->video_dev);
2427 + if (unicam->sensor_config)
2428 + v4l2_subdev_free_pad_config(unicam->sensor_config);
2429 + media_device_unregister(&unicam->mdev);
2430 + media_device_cleanup(&unicam->mdev);
2431 +
2432 + return 0;
2433 +}
2434 +
2435 +static const struct of_device_id unicam_of_match[] = {
2436 + { .compatible = "brcm,bcm2835-unicam", },
2437 + { /* sentinel */ },
2438 +};
2439 +MODULE_DEVICE_TABLE(of, unicam_of_match);
2440 +
2441 +static struct platform_driver unicam_driver = {
2442 + .probe = unicam_probe,
2443 + .remove = unicam_remove,
2444 + .driver = {
2445 + .name = UNICAM_MODULE_NAME,
2446 + .of_match_table = of_match_ptr(unicam_of_match),
2447 + },
2448 +};
2449 +
2450 +module_platform_driver(unicam_driver);
2451 +
2452 +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com>");
2453 +MODULE_DESCRIPTION("BCM2835 Unicam driver");
2454 +MODULE_LICENSE("GPL");
2455 +MODULE_VERSION(UNICAM_VERSION);
2456 --- /dev/null
2457 +++ b/drivers/media/platform/bcm2835/vc4-regs-unicam.h
2458 @@ -0,0 +1,253 @@
2459 +/* SPDX-License-Identifier: GPL-2.0-only */
2460 +
2461 +/*
2462 + * Copyright (C) 2017-2020 Raspberry Pi Trading.
2463 + * Dave Stevenson <dave.stevenson@raspberrypi.com>
2464 + */
2465 +
2466 +#ifndef VC4_REGS_UNICAM_H
2467 +#define VC4_REGS_UNICAM_H
2468 +
2469 +/*
2470 + * The following values are taken from files found within the code drop
2471 + * made by Broadcom for the BCM21553 Graphics Driver, predominantly in
2472 + * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.
2473 + * They have been modified to be only the register offset.
2474 + */
2475 +#define UNICAM_CTRL 0x000
2476 +#define UNICAM_STA 0x004
2477 +#define UNICAM_ANA 0x008
2478 +#define UNICAM_PRI 0x00c
2479 +#define UNICAM_CLK 0x010
2480 +#define UNICAM_CLT 0x014
2481 +#define UNICAM_DAT0 0x018
2482 +#define UNICAM_DAT1 0x01c
2483 +#define UNICAM_DAT2 0x020
2484 +#define UNICAM_DAT3 0x024
2485 +#define UNICAM_DLT 0x028
2486 +#define UNICAM_CMP0 0x02c
2487 +#define UNICAM_CMP1 0x030
2488 +#define UNICAM_CAP0 0x034
2489 +#define UNICAM_CAP1 0x038
2490 +#define UNICAM_ICTL 0x100
2491 +#define UNICAM_ISTA 0x104
2492 +#define UNICAM_IDI0 0x108
2493 +#define UNICAM_IPIPE 0x10c
2494 +#define UNICAM_IBSA0 0x110
2495 +#define UNICAM_IBEA0 0x114
2496 +#define UNICAM_IBLS 0x118
2497 +#define UNICAM_IBWP 0x11c
2498 +#define UNICAM_IHWIN 0x120
2499 +#define UNICAM_IHSTA 0x124
2500 +#define UNICAM_IVWIN 0x128
2501 +#define UNICAM_IVSTA 0x12c
2502 +#define UNICAM_ICC 0x130
2503 +#define UNICAM_ICS 0x134
2504 +#define UNICAM_IDC 0x138
2505 +#define UNICAM_IDPO 0x13c
2506 +#define UNICAM_IDCA 0x140
2507 +#define UNICAM_IDCD 0x144
2508 +#define UNICAM_IDS 0x148
2509 +#define UNICAM_DCS 0x200
2510 +#define UNICAM_DBSA0 0x204
2511 +#define UNICAM_DBEA0 0x208
2512 +#define UNICAM_DBWP 0x20c
2513 +#define UNICAM_DBCTL 0x300
2514 +#define UNICAM_IBSA1 0x304
2515 +#define UNICAM_IBEA1 0x308
2516 +#define UNICAM_IDI1 0x30c
2517 +#define UNICAM_DBSA1 0x310
2518 +#define UNICAM_DBEA1 0x314
2519 +#define UNICAM_MISC 0x400
2520 +
2521 +/*
2522 + * The following bitmasks are from the kernel released by Broadcom
2523 + * for Android - https://android.googlesource.com/kernel/bcm/
2524 + * The Rhea, Hawaii, and Java chips all contain the same VideoCore4
2525 + * Unicam block as BCM2835, as defined in eg
2526 + * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.
2527 + * Values reworked to use the kernel BIT and GENMASK macros.
2528 + *
2529 + * Some of the bit mnenomics have been amended to match the datasheet.
2530 + */
2531 +/* UNICAM_CTRL Register */
2532 +#define UNICAM_CPE BIT(0)
2533 +#define UNICAM_MEM BIT(1)
2534 +#define UNICAM_CPR BIT(2)
2535 +#define UNICAM_CPM_MASK GENMASK(3, 3)
2536 +#define UNICAM_CPM_CSI2 0
2537 +#define UNICAM_CPM_CCP2 1
2538 +#define UNICAM_SOE BIT(4)
2539 +#define UNICAM_DCM_MASK GENMASK(5, 5)
2540 +#define UNICAM_DCM_STROBE 0
2541 +#define UNICAM_DCM_DATA 1
2542 +#define UNICAM_SLS BIT(6)
2543 +#define UNICAM_PFT_MASK GENMASK(11, 8)
2544 +#define UNICAM_OET_MASK GENMASK(20, 12)
2545 +
2546 +/* UNICAM_STA Register */
2547 +#define UNICAM_SYN BIT(0)
2548 +#define UNICAM_CS BIT(1)
2549 +#define UNICAM_SBE BIT(2)
2550 +#define UNICAM_PBE BIT(3)
2551 +#define UNICAM_HOE BIT(4)
2552 +#define UNICAM_PLE BIT(5)
2553 +#define UNICAM_SSC BIT(6)
2554 +#define UNICAM_CRCE BIT(7)
2555 +#define UNICAM_OES BIT(8)
2556 +#define UNICAM_IFO BIT(9)
2557 +#define UNICAM_OFO BIT(10)
2558 +#define UNICAM_BFO BIT(11)
2559 +#define UNICAM_DL BIT(12)
2560 +#define UNICAM_PS BIT(13)
2561 +#define UNICAM_IS BIT(14)
2562 +#define UNICAM_PI0 BIT(15)
2563 +#define UNICAM_PI1 BIT(16)
2564 +#define UNICAM_FSI_S BIT(17)
2565 +#define UNICAM_FEI_S BIT(18)
2566 +#define UNICAM_LCI_S BIT(19)
2567 +#define UNICAM_BUF0_RDY BIT(20)
2568 +#define UNICAM_BUF0_NO BIT(21)
2569 +#define UNICAM_BUF1_RDY BIT(22)
2570 +#define UNICAM_BUF1_NO BIT(23)
2571 +#define UNICAM_DI BIT(24)
2572 +
2573 +#define UNICAM_STA_MASK_ALL \
2574 + (UNICAM_DL + \
2575 + UNICAM_SBE + \
2576 + UNICAM_PBE + \
2577 + UNICAM_HOE + \
2578 + UNICAM_PLE + \
2579 + UNICAM_SSC + \
2580 + UNICAM_CRCE + \
2581 + UNICAM_IFO + \
2582 + UNICAM_OFO + \
2583 + UNICAM_PS + \
2584 + UNICAM_PI0 + \
2585 + UNICAM_PI1)
2586 +
2587 +/* UNICAM_ANA Register */
2588 +#define UNICAM_APD BIT(0)
2589 +#define UNICAM_BPD BIT(1)
2590 +#define UNICAM_AR BIT(2)
2591 +#define UNICAM_DDL BIT(3)
2592 +#define UNICAM_CTATADJ_MASK GENMASK(7, 4)
2593 +#define UNICAM_PTATADJ_MASK GENMASK(11, 8)
2594 +
2595 +/* UNICAM_PRI Register */
2596 +#define UNICAM_PE BIT(0)
2597 +#define UNICAM_PT_MASK GENMASK(2, 1)
2598 +#define UNICAM_NP_MASK GENMASK(7, 4)
2599 +#define UNICAM_PP_MASK GENMASK(11, 8)
2600 +#define UNICAM_BS_MASK GENMASK(15, 12)
2601 +#define UNICAM_BL_MASK GENMASK(17, 16)
2602 +
2603 +/* UNICAM_CLK Register */
2604 +#define UNICAM_CLE BIT(0)
2605 +#define UNICAM_CLPD BIT(1)
2606 +#define UNICAM_CLLPE BIT(2)
2607 +#define UNICAM_CLHSE BIT(3)
2608 +#define UNICAM_CLTRE BIT(4)
2609 +#define UNICAM_CLAC_MASK GENMASK(8, 5)
2610 +#define UNICAM_CLSTE BIT(29)
2611 +
2612 +/* UNICAM_CLT Register */
2613 +#define UNICAM_CLT1_MASK GENMASK(7, 0)
2614 +#define UNICAM_CLT2_MASK GENMASK(15, 8)
2615 +
2616 +/* UNICAM_DATn Registers */
2617 +#define UNICAM_DLE BIT(0)
2618 +#define UNICAM_DLPD BIT(1)
2619 +#define UNICAM_DLLPE BIT(2)
2620 +#define UNICAM_DLHSE BIT(3)
2621 +#define UNICAM_DLTRE BIT(4)
2622 +#define UNICAM_DLSM BIT(5)
2623 +#define UNICAM_DLFO BIT(28)
2624 +#define UNICAM_DLSTE BIT(29)
2625 +
2626 +#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)
2627 +
2628 +/* UNICAM_DLT Register */
2629 +#define UNICAM_DLT1_MASK GENMASK(7, 0)
2630 +#define UNICAM_DLT2_MASK GENMASK(15, 8)
2631 +#define UNICAM_DLT3_MASK GENMASK(23, 16)
2632 +
2633 +/* UNICAM_ICTL Register */
2634 +#define UNICAM_FSIE BIT(0)
2635 +#define UNICAM_FEIE BIT(1)
2636 +#define UNICAM_IBOB BIT(2)
2637 +#define UNICAM_FCM BIT(3)
2638 +#define UNICAM_TFC BIT(4)
2639 +#define UNICAM_LIP_MASK GENMASK(6, 5)
2640 +#define UNICAM_LCIE_MASK GENMASK(28, 16)
2641 +
2642 +/* UNICAM_IDI0/1 Register */
2643 +#define UNICAM_ID0_MASK GENMASK(7, 0)
2644 +#define UNICAM_ID1_MASK GENMASK(15, 8)
2645 +#define UNICAM_ID2_MASK GENMASK(23, 16)
2646 +#define UNICAM_ID3_MASK GENMASK(31, 24)
2647 +
2648 +/* UNICAM_ISTA Register */
2649 +#define UNICAM_FSI BIT(0)
2650 +#define UNICAM_FEI BIT(1)
2651 +#define UNICAM_LCI BIT(2)
2652 +
2653 +#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)
2654 +
2655 +/* UNICAM_IPIPE Register */
2656 +#define UNICAM_PUM_MASK GENMASK(2, 0)
2657 + /* Unpacking modes */
2658 + #define UNICAM_PUM_NONE 0
2659 + #define UNICAM_PUM_UNPACK6 1
2660 + #define UNICAM_PUM_UNPACK7 2
2661 + #define UNICAM_PUM_UNPACK8 3
2662 + #define UNICAM_PUM_UNPACK10 4
2663 + #define UNICAM_PUM_UNPACK12 5
2664 + #define UNICAM_PUM_UNPACK14 6
2665 + #define UNICAM_PUM_UNPACK16 7
2666 +#define UNICAM_DDM_MASK GENMASK(6, 3)
2667 +#define UNICAM_PPM_MASK GENMASK(9, 7)
2668 + /* Packing modes */
2669 + #define UNICAM_PPM_NONE 0
2670 + #define UNICAM_PPM_PACK8 1
2671 + #define UNICAM_PPM_PACK10 2
2672 + #define UNICAM_PPM_PACK12 3
2673 + #define UNICAM_PPM_PACK14 4
2674 + #define UNICAM_PPM_PACK16 5
2675 +#define UNICAM_DEM_MASK GENMASK(11, 10)
2676 +#define UNICAM_DEBL_MASK GENMASK(14, 12)
2677 +#define UNICAM_ICM_MASK GENMASK(16, 15)
2678 +#define UNICAM_IDM_MASK GENMASK(17, 17)
2679 +
2680 +/* UNICAM_ICC Register */
2681 +#define UNICAM_ICFL_MASK GENMASK(4, 0)
2682 +#define UNICAM_ICFH_MASK GENMASK(9, 5)
2683 +#define UNICAM_ICST_MASK GENMASK(12, 10)
2684 +#define UNICAM_ICLT_MASK GENMASK(15, 13)
2685 +#define UNICAM_ICLL_MASK GENMASK(31, 16)
2686 +
2687 +/* UNICAM_DCS Register */
2688 +#define UNICAM_DIE BIT(0)
2689 +#define UNICAM_DIM BIT(1)
2690 +#define UNICAM_DBOB BIT(3)
2691 +#define UNICAM_FDE BIT(4)
2692 +#define UNICAM_LDP BIT(5)
2693 +#define UNICAM_EDL_MASK GENMASK(15, 8)
2694 +
2695 +/* UNICAM_DBCTL Register */
2696 +#define UNICAM_DBEN BIT(0)
2697 +#define UNICAM_BUF0_IE BIT(1)
2698 +#define UNICAM_BUF1_IE BIT(2)
2699 +
2700 +/* UNICAM_CMP[0,1] register */
2701 +#define UNICAM_PCE BIT(31)
2702 +#define UNICAM_GI BIT(9)
2703 +#define UNICAM_CPH BIT(8)
2704 +#define UNICAM_PCVC_MASK GENMASK(7, 6)
2705 +#define UNICAM_PCDT_MASK GENMASK(5, 0)
2706 +
2707 +/* UNICAM_MISC register */
2708 +#define UNICAM_FL0 BIT(6)
2709 +#define UNICAM_FL1 BIT(9)
2710 +
2711 +#endif
OpenWrt Source Repository