bcm27xx: add kernel 5.10 support
[openwrt/openwrt.git] / target / linux / bcm27xx / patches-5.10 / 950-0615-media-rpivid-Map-cmd-buffer-directly.patch
1 From d4f8e47d60c180cf57eba4093a343230a824ecbf Mon Sep 17 00:00:00 2001
2 From: John Cox <jc@kynesim.co.uk>
3 Date: Mon, 29 Mar 2021 17:42:16 +0100
4 Subject: [PATCH] media: rpivid: Map cmd buffer directly
5
6 It is unnecessary to have a separate dmabuf to hold the cmd buffer.
7 Map it directly from the kmalloc.
8
9 Signed-off-by: John Cox <jc@kynesim.co.uk>
10 ---
11 drivers/staging/media/rpivid/rpivid.h | 3 +-
12 drivers/staging/media/rpivid/rpivid_h265.c | 48 ++++++++++------------
13 drivers/staging/media/rpivid/rpivid_hw.c | 2 +
14 3 files changed, 25 insertions(+), 28 deletions(-)
15
16 --- a/drivers/staging/media/rpivid/rpivid.h
17 +++ b/drivers/staging/media/rpivid/rpivid.h
18 @@ -114,7 +114,6 @@ struct rpivid_ctx {
19 unsigned int p1idx;
20 atomic_t p1out;
21 struct rpivid_gptr bitbufs[RPIVID_P1BUF_COUNT];
22 - struct rpivid_gptr cmdbufs[RPIVID_P1BUF_COUNT];
23
24 /* *** Should be in dev *** */
25 unsigned int p2idx;
26 @@ -183,6 +182,8 @@ struct rpivid_dev {
27 struct clk *clock;
28 struct clk_request *hevc_req;
29
30 + int cache_align;
31 +
32 struct rpivid_hw_irq_ctrl ic_active1;
33 struct rpivid_hw_irq_ctrl ic_active2;
34 };
35 --- a/drivers/staging/media/rpivid/rpivid_h265.c
36 +++ b/drivers/staging/media/rpivid/rpivid_h265.c
37 @@ -227,6 +227,9 @@ struct rpivid_dec_env {
38 struct rpivid_q_aux *frame_aux;
39 struct rpivid_q_aux *col_aux;
40
41 + dma_addr_t cmd_addr;
42 + size_t cmd_size;
43 +
44 dma_addr_t pu_base_vc;
45 dma_addr_t coeff_base_vc;
46 u32 pu_stride;
47 @@ -234,7 +237,6 @@ struct rpivid_dec_env {
48
49 struct rpivid_gptr *bit_copy_gptr;
50 size_t bit_copy_len;
51 - struct rpivid_gptr *cmd_copy_gptr;
52
53 #define SLICE_MSGS_MAX (2 * HEVC_MAX_REFS * 8 + 3)
54 u16 slice_msgs[SLICE_MSGS_MAX];
55 @@ -1499,22 +1501,17 @@ static int write_cmd_buffer(struct rpivi
56 struct rpivid_dec_env *const de,
57 const struct rpivid_dec_state *const s)
58 {
59 - // Copy commands out to dma buf
60 - const size_t cmd_size = de->cmd_len * sizeof(de->cmd_fifo[0]);
61 -
62 - if (!de->cmd_copy_gptr->ptr || cmd_size > de->cmd_copy_gptr->size) {
63 - size_t cmd_alloc = round_up_size(cmd_size);
64 + const size_t cmd_size = ALIGN(de->cmd_len * sizeof(de->cmd_fifo[0]),
65 + dev->cache_align);
66
67 - if (gptr_realloc_new(dev, de->cmd_copy_gptr, cmd_alloc)) {
68 - v4l2_err(&dev->v4l2_dev,
69 - "Alloc cmd buffer (%zu): FAILED\n", cmd_alloc);
70 - return -ENOMEM;
71 - }
72 - v4l2_info(&dev->v4l2_dev, "Alloc cmd buffer (%zu): OK\n",
73 - cmd_alloc);
74 + de->cmd_addr = dma_map_single(dev->dev, de->cmd_fifo,
75 + cmd_size, DMA_TO_DEVICE);
76 + if (dma_mapping_error(dev->dev, de->cmd_addr)) {
77 + v4l2_err(&dev->v4l2_dev,
78 + "Map cmd buffer (%zu): FAILED\n", cmd_size);
79 + return -ENOMEM;
80 }
81 -
82 - memcpy(de->cmd_copy_gptr->ptr, de->cmd_fifo, cmd_size);
83 + de->cmd_size = cmd_size;
84 return 0;
85 }
86
87 @@ -1551,6 +1548,12 @@ static void dec_env_delete(struct rpivid
88 struct rpivid_ctx * const ctx = de->ctx;
89 unsigned long lock_flags;
90
91 + if (de->cmd_size) {
92 + dma_unmap_single(ctx->dev->dev, de->cmd_addr, de->cmd_size,
93 + DMA_TO_DEVICE);
94 + de->cmd_size = 0;
95 + }
96 +
97 aux_q_release(ctx, &de->frame_aux);
98 aux_q_release(ctx, &de->col_aux);
99
100 @@ -1603,7 +1606,8 @@ static int dec_env_init(struct rpivid_ct
101
102 de->ctx = ctx;
103 de->decode_order = i;
104 - de->cmd_max = 1024;
105 +// de->cmd_max = 1024;
106 + de->cmd_max = 8096;
107 de->cmd_fifo = kmalloc_array(de->cmd_max,
108 sizeof(struct rpi_cmd),
109 GFP_KERNEL);
110 @@ -1748,7 +1752,6 @@ static void rpivid_h265_setup(struct rpi
111
112 de->bit_copy_gptr = ctx->bitbufs + ctx->p1idx;
113 de->bit_copy_len = 0;
114 - de->cmd_copy_gptr = ctx->cmdbufs + ctx->p1idx;
115
116 de->frame_c_offset = ctx->dst_fmt.height * 128;
117 de->frame_stride = ctx->dst_fmt.plane_fmt[0].bytesperline * 128;
118 @@ -2356,7 +2359,7 @@ static void phase1_claimed(struct rpivid
119 rpivid_hw_irq_active1_irq(dev, &de->irq_ent, phase1_cb, de);
120
121 // And start the h/w
122 - apb_write_vc_addr_final(dev, RPI_CFBASE, de->cmd_copy_gptr->addr);
123 + apb_write_vc_addr_final(dev, RPI_CFBASE, de->cmd_addr);
124
125 xtrace_ok(dev, de);
126 return;
127 @@ -2400,8 +2403,6 @@ static void rpivid_h265_stop(struct rpiv
128
129 for (i = 0; i != ARRAY_SIZE(ctx->bitbufs); ++i)
130 gptr_free(dev, ctx->bitbufs + i);
131 - for (i = 0; i != ARRAY_SIZE(ctx->cmdbufs); ++i)
132 - gptr_free(dev, ctx->cmdbufs + i);
133 for (i = 0; i != ARRAY_SIZE(ctx->pu_bufs); ++i)
134 gptr_free(dev, ctx->pu_bufs + i);
135 for (i = 0; i != ARRAY_SIZE(ctx->coeff_bufs); ++i)
136 @@ -2451,13 +2452,6 @@ static int rpivid_h265_start(struct rpiv
137 goto fail;
138 }
139
140 - // 16k is plenty for most purposes but we will realloc if needed
141 - for (i = 0; i != ARRAY_SIZE(ctx->cmdbufs); ++i) {
142 - if (gptr_alloc(dev, ctx->cmdbufs + i, 0x4000,
143 - DMA_ATTR_FORCE_CONTIGUOUS))
144 - goto fail;
145 - }
146 -
147 // Finger in the air PU & Coeff alloc
148 // Will be realloced if too small
149 coeff_alloc = round_up_size(wxh);
150 --- a/drivers/staging/media/rpivid/rpivid_hw.c
151 +++ b/drivers/staging/media/rpivid/rpivid_hw.c
152 @@ -331,6 +331,8 @@ int rpivid_hw_probe(struct rpivid_dev *d
153 if (IS_ERR(dev->clock))
154 return PTR_ERR(dev->clock);
155
156 + dev->cache_align = dma_get_cache_alignment();
157 +
158 // Disable IRQs & reset anything pending
159 irq_write(dev, 0,
160 ARG_IC_ICTRL_ACTIVE1_EN_SET | ARG_IC_ICTRL_ACTIVE2_EN_SET);