target/linux/bcm27xx/patches-4.19/950-0343-ASoC-tlv320aic32x4-Properly-Set-Processing-Blocks.patch

   1 From 6cc882cf38b62fce2a07640413b05b43b420c77a Mon Sep 17 00:00:00 2001
   2 From: Annaliese McDermond <nh6z@nh6z.net>
   3 Date: Wed, 20 Mar 2019 19:38:44 -0700
   4 Subject: [PATCH] ASoC: tlv320aic32x4: Properly Set Processing Blocks
   5
   6 commit c95e3a4b96293403a427b5185e60fad28af51fdd upstream.
   7
   8 Different processing blocks are required for different sampling
   9 rates and power parameters.  Set the processing blocks based
  10 on this information.
  11
  12 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
  13 Signed-off-by: Mark Brown <broonie@kernel.org>
  14 ---
  15  sound/soc/codecs/tlv320aic32x4.c | 56 ++++++++++++++++++++------------
  16  1 file changed, 36 insertions(+), 20 deletions(-)
  17
  18 --- a/sound/soc/codecs/tlv320aic32x4.c
  19 +++ b/sound/soc/codecs/tlv320aic32x4.c
  20 @@ -59,6 +59,8 @@ struct aic32x4_rate_divs {
  21         u8 nadc;
  22         u8 madc;
  23         u8 blck_N;
  24 +       u8 r_block;
  25 +       u8 p_block;
  26  };
  27
  28  struct aic32x4_priv {
  29 @@ -307,34 +309,34 @@ static const struct snd_kcontrol_new aic
  30
  31  static const struct aic32x4_rate_divs aic32x4_divs[] = {
  32         /* 8k rate */
  33 -       {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
  34 -       {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
  35 -       {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
  36 +       {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24, 1, 1},
  37 +       {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24, 1, 1},
  38 +       {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24, 1, 1},
  39         /* 11.025k rate */
  40 -       {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
  41 -       {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
  42 +       {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16, 1, 1},
  43 +       {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16, 1, 1},
  44         /* 16k rate */
  45 -       {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
  46 -       {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
  47 -       {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
  48 +       {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12, 1, 1},
  49 +       {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12, 1, 1},
  50 +       {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12, 1, 1},
  51         /* 22.05k rate */
  52 -       {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
  53 -       {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
  54 -       {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
  55 +       {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8, 1, 1},
  56 +       {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8, 1, 1},
  57 +       {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8, 1, 1},
  58         /* 32k rate */
  59 -       {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
  60 -       {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
  61 +       {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6, 1, 1},
  62 +       {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6, 1, 1},
  63         /* 44.1k rate */
  64 -       {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
  65 -       {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
  66 -       {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
  67 +       {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4, 1, 1},
  68 +       {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4, 1, 1},
  69 +       {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4, 1, 1},
  70         /* 48k rate */
  71 -       {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
  72 -       {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
  73 -       {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4},
  74 +       {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4, 1, 1},
  75 +       {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4, 1, 1},
  76 +       {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4, 1, 1},
  77
  78         /* 96k rate */
  79 -       {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1},
  80 +       {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1, 1, 9},
  81  };
  82
  83  static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
  84 @@ -698,6 +700,18 @@ static int aic32x4_set_dai_fmt(struct sn
  85         return 0;
  86  }
  87
  88 +static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
  89 +                                               u8 r_block, u8 p_block)
  90 +{
  91 +       if (r_block > 18 || p_block > 25)
  92 +               return -EINVAL;
  93 +
  94 +       snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
  95 +       snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
  96 +
  97 +       return 0;
  98 +}
  99 +
 100  static int aic32x4_setup_clocks(struct snd_soc_component *component,
 101                                 unsigned int sample_rate,
 102                                 unsigned int parent_rate)
 103 @@ -710,6 +724,8 @@ static int aic32x4_setup_clocks(struct s
 104                 return i;
 105         }
 106
 107 +       aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
 108 +
 109         /* MCLK as PLL_CLKIN */
 110         snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
 111                             AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);