target/linux/ath79/patches-5.10/0039-MIPS-ath79-export-UART1-reference-clock.patch

   1 From: Daniel Golle <daniel@makrotopia.org>
   2 Subject: [PATCH] ath79: add support for Atheros AR934x HS UART
   3
   4 AR934x chips also got the 'old' qca,ar9330-uart in addition to the
   5 'new' ns16550a compatible one. Add support for UART1 clock selector as
   6 well as device-tree bindings in ar934x.dtsi to make use of that uart.
   7
   8 Reported-by: Piotr Dymacz <pepe2k@gmail.com>
   9 Submitted-by: Daniel Golle <daniel@makrotopia.org>
  10 ---
  11  arch/mips/ath79/clock.c                       | 7 +++++++
  12  .../mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
  13  include/dt-bindings/clock/ath79-clk.h         | 3 ++-
  14  3 files changed, 10 insertions(+), 1 deletion(-)
  15
  16 --- a/arch/mips/ath79/clock.c
  17 +++ b/arch/mips/ath79/clock.c
  18 @@ -40,6 +40,7 @@ static const char * const clk_names[ATH7
  19         [ATH79_CLK_AHB] = "ahb",
  20         [ATH79_CLK_REF] = "ref",
  21         [ATH79_CLK_MDIO] = "mdio",
  22 +       [ATH79_CLK_UART1] = "uart1",
  23  };
  24
  25  static const char * __init ath79_clk_name(int type)
  26 @@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo
  27         if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
  28                 ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
  29
  30 +       if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
  31 +               ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
  32 +
  33         iounmap(dpll_base);
  34  }
  35
  36 @@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt(
  37         if (!clks[ATH79_CLK_MDIO])
  38                 clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
  39
  40 +       if (!clks[ATH79_CLK_UART1])
  41 +               clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
  42 +
  43         if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
  44                 pr_err("%pOF: could not register clk provider\n", np);
  45                 goto err_iounmap;
  46 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  47 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  48 @@ -348,6 +348,7 @@
  49  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  50
  51  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
  52 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL  BIT(7)
  53
  54  #define QCA953X_PLL_CPU_CONFIG_REG             0x00
  55  #define QCA953X_PLL_DDR_CONFIG_REG             0x04
  56 --- a/include/dt-bindings/clock/ath79-clk.h
  57 +++ b/include/dt-bindings/clock/ath79-clk.h
  58 @@ -11,7 +11,8 @@
  59  #define ATH79_CLK_AHB          2
  60  #define ATH79_CLK_REF          3
  61  #define ATH79_CLK_MDIO         4
  62 +#define ATH79_CLK_UART1                5
  63
  64 -#define ATH79_CLK_END          5
  65 +#define ATH79_CLK_END          6
  66
  67  #endif /* __DT_BINDINGS_ATH79_CLK_H */