target/linux/at91/patches-5.15/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch

   1 From 91a49481af7332853c4c921d46aded8210572210 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Mon, 11 Oct 2021 14:27:17 +0300
   4 Subject: [PATCH 245/247] clk: at91: sama7g5: remove prescaler part of master
   5  clock
   6
   7 On SAMA7G5 the prescaler part of master clock has been implemented as a
   8 changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit
   9 must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is
  10 done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has
  11 been discovered that in some conditions the PMC_SR.MCKRDY is not rising
  12 but the rate it provides it's stable. The workaround is to add a timeout
  13 when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler
  14 will be removed from Linux clock tree as all the frequencies for CPU could
  15 be obtained from PLL and also there will be less overhead when changing
  16 frequency via DVFS.
  17
  18 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  19 Link: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.com
  20 Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  21 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  22 ---
  23  drivers/clk/at91/sama7g5.c | 11 +----------
  24  1 file changed, 1 insertion(+), 10 deletions(-)
  25
  26 --- a/drivers/clk/at91/sama7g5.c
  27 +++ b/drivers/clk/at91/sama7g5.c
  28 @@ -992,16 +992,7 @@ static void __init sama7g5_pmc_setup(str
  29         }
  30
  31         parent_names[0] = "cpupll_divpmcck";
  32 -       hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
  33 -                                          &mck0_layout, &mck0_characteristics,
  34 -                                          &pmc_mck0_lock,
  35 -                                          CLK_SET_RATE_PARENT, 0);
  36 -       if (IS_ERR(hw))
  37 -               goto err_free;
  38 -
  39 -       sama7g5_pmc->chws[PMC_CPU] = hw;
  40 -
  41 -       hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
  42 +       hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
  43                                           &mck0_layout, &mck0_characteristics,
  44                                           &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
  45         if (IS_ERR(hw))