target/linux/at91/patches-5.15/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch

   1 From 8b88f1e9918c173b24b43015cdb713cdde9e4d17 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Thu, 19 Nov 2020 17:43:14 +0200
   4 Subject: [PATCH 108/247] clk: at91: sama7g5: decrease lower limit for MCK0
   5  rate
   6
   7 On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
   8 CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
   9 also changed by DVFS to avoid over/under clocking of MCK0 consumers.
  10 The lower limit is changed to be able to set MCK0 accordingly by
  11 DVFS.
  12
  13 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  14 Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  drivers/clk/at91/sama7g5.c | 2 +-
  18  1 file changed, 1 insertion(+), 1 deletion(-)
  19
  20 --- a/drivers/clk/at91/sama7g5.c
  21 +++ b/drivers/clk/at91/sama7g5.c
  22 @@ -807,7 +807,7 @@ static const struct clk_pll_characterist
  23
  24  /* MCK0 characteristics. */
  25  static const struct clk_master_characteristics mck0_characteristics = {
  26 -       .output = { .min = 140000000, .max = 200000000 },
  27 +       .output = { .min = 50000000, .max = 200000000 },
  28         .divisors = { 1, 2, 4, 3, 5 },
  29         .have_div3_pres = 1,
  30  };