target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch

   1 From 4375cd63b55860f5e82618dc5f50846b3129842a Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Mon, 11 Oct 2021 14:27:14 +0300
   4 Subject: [PATCH 242/247] clk: at91: clk-master: fix prescaler logic
   5
   6 When prescaler value read from register is MASTER_PRES_MAX it means
   7 that the input clock will be divided by 3. Fix the code to reflect
   8 this.
   9
  10 Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
  11 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  12 Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com
  13 Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  14 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  15 ---
  16  drivers/clk/at91/clk-master.c | 2 +-
  17  1 file changed, 1 insertion(+), 1 deletion(-)
  18
  19 diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
  20 index 6da9ae34313a..e67bcd03a827 100644
  21 --- a/drivers/clk/at91/clk-master.c
  22 +++ b/drivers/clk/at91/clk-master.c
  23 @@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
  24
  25         val &= master->layout->mask;
  26         pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
  27 -       if (pres == 3 && characteristics->have_div3_pres)
  28 +       if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
  29                 pres = 3;
  30         else
  31                 pres = (1 << pres);
  32 --
  33 2.32.0
  34