target/linux/at91/patches-5.10/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch

   1 From 4c0b77276307d2cba8ae2595cbae4cc916c84c36 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Wed, 15 Sep 2021 10:48:36 +0300
   4 Subject: [PATCH 233/247] ARM: dts: at91: sama7g5ek: to not touch slew-rate for
   5  SDMMC pins
   6
   7 With commit c709135e576b ("pinctrl: at91-pio4: add support for slew-rate")
   8 and commit cbde6c823bfa ("pinctrl: at91-pio4: Fix slew rate disablement")
   9 the slew-rate is enabled by default for each configured pin. The datasheet
  10 specifies at chapter "Output Driver AC Characteristics" that HSIO
  11 drivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate
  12 setting but are rather calibrated against an external 1% resistor mounted
  13 on the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal
  14 frequency and the external load, it is possible to adjust their target
  15 output impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled
  16 at the moment in device tree).
  17
  18 Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
  19 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  20 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  21 Link: https://lore.kernel.org/r/20210915074836.6574-3-claudiu.beznea@microchip.com
  22 ---
  23  arch/arm/boot/dts/at91-sama7g5ek.dts | 6 ++++++
  24  1 file changed, 6 insertions(+)
  25
  26 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts
  27 +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
  28 @@ -558,6 +558,7 @@
  29                                  <PIN_PA8__SDMMC0_DAT5>,
  30                                  <PIN_PA9__SDMMC0_DAT6>,
  31                                  <PIN_PA10__SDMMC0_DAT7>;
  32 +                       slew-rate = <0>;
  33                         bias-pull-up;
  34                 };
  35
  36 @@ -565,6 +566,7 @@
  37                         pinmux = <PIN_PA0__SDMMC0_CK>,
  38                                  <PIN_PA2__SDMMC0_RSTN>,
  39                                  <PIN_PA11__SDMMC0_DS>;
  40 +                       slew-rate = <0>;
  41                         bias-pull-up;
  42                 };
  43         };
  44 @@ -576,6 +578,7 @@
  45                                  <PIN_PC0__SDMMC1_DAT1>,
  46                                  <PIN_PC1__SDMMC1_DAT2>,
  47                                  <PIN_PC2__SDMMC1_DAT3>;
  48 +                       slew-rate = <0>;
  49                         bias-pull-up;
  50                 };
  51
  52 @@ -584,6 +587,7 @@
  53                                  <PIN_PB28__SDMMC1_RSTN>,
  54                                  <PIN_PC5__SDMMC1_1V8SEL>,
  55                                  <PIN_PC4__SDMMC1_CD>;
  56 +                       slew-rate = <0>;
  57                         bias-pull-up;
  58                 };
  59         };
  60 @@ -595,11 +599,13 @@
  61                                  <PIN_PD6__SDMMC2_DAT1>,
  62                                  <PIN_PD7__SDMMC2_DAT2>,
  63                                  <PIN_PD8__SDMMC2_DAT3>;
  64 +                       slew-rate = <0>;
  65                         bias-pull-up;
  66                 };
  67
  68                 ck {
  69                         pinmux = <PIN_PD4__SDMMC2_CK>;
  70 +                       slew-rate = <0>;
  71                         bias-pull-up;
  72                 };
  73         };