target/linux/at91/patches-5.10/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch

   1 From bf032d1a0105939b90072914d88181fbe6187f43 Mon Sep 17 00:00:00 2001
   2 From: Eugen Hristev <eugen.hristev@microchip.com>
   3 Date: Tue, 13 Apr 2021 12:57:24 +0200
   4 Subject: [PATCH 182/247] media: atmel: atmel-isc-regs: add additional fields
   5  for sama7g5 type pipeline
   6
   7 Add additional fields for registers present in sama7g5 type pipeline.
   8 Extend register masks for additional bits in sama7g5 type pipeline registers.
   9
  10 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
  11 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
  12 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
  13 ---
  14  drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++--
  15  1 file changed, 14 insertions(+), 2 deletions(-)
  16
  17 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
  18 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
  19 @@ -289,8 +289,18 @@
  20  #define ISC_RLP_CFG_MODE_ARGB32         0xa
  21  #define ISC_RLP_CFG_MODE_YYCC           0xb
  22  #define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc
  23 +#define ISC_RLP_CFG_MODE_YCYC           0xd
  24  #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)
  25
  26 +#define ISC_RLP_CFG_LSH                        BIT(5)
  27 +
  28 +#define ISC_RLP_CFG_YMODE_YUYV         (3 << 6)
  29 +#define ISC_RLP_CFG_YMODE_YVYU         (2 << 6)
  30 +#define ISC_RLP_CFG_YMODE_VYUY         (0 << 6)
  31 +#define ISC_RLP_CFG_YMODE_UYVY         (1 << 6)
  32 +
  33 +#define ISC_RLP_CFG_YMODE_MASK         GENMASK(7, 6)
  34 +
  35  /* Offset for HIS register specific to sama5d2 product */
  36  #define ISC_SAMA5D2_HIS_OFFSET 0
  37  /* Histogram Control Register */
  38 @@ -332,13 +342,15 @@
  39  #define ISC_DCFG_YMBSIZE_BEATS4         (0x1 << 4)
  40  #define ISC_DCFG_YMBSIZE_BEATS8         (0x2 << 4)
  41  #define ISC_DCFG_YMBSIZE_BEATS16        (0x3 << 4)
  42 -#define ISC_DCFG_YMBSIZE_MASK           GENMASK(5, 4)
  43 +#define ISC_DCFG_YMBSIZE_BEATS32        (0x4 << 4)
  44 +#define ISC_DCFG_YMBSIZE_MASK           GENMASK(6, 4)
  45
  46  #define ISC_DCFG_CMBSIZE_SINGLE         (0x0 << 8)
  47  #define ISC_DCFG_CMBSIZE_BEATS4         (0x1 << 8)
  48  #define ISC_DCFG_CMBSIZE_BEATS8         (0x2 << 8)
  49  #define ISC_DCFG_CMBSIZE_BEATS16        (0x3 << 8)
  50 -#define ISC_DCFG_CMBSIZE_MASK           GENMASK(9, 8)
  51 +#define ISC_DCFG_CMBSIZE_BEATS32        (0x4 << 8)
  52 +#define ISC_DCFG_CMBSIZE_MASK           GENMASK(10, 8)
  53
  54  /* DMA Control Register */
  55  #define ISC_DCTRL       0x000003e4