target/linux/at91/patches-5.10/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch

   1 From 5f090a664d62ceeaf9a0f482426e35cab18d65a9 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Tue, 19 Jan 2021 14:59:25 +0200
   4 Subject: [PATCH 143/247] clocksource/drivers/timer-microchip-pit64b: Add
   5  clocksource suspend/resume
   6
   7 Add suspend/resume support for clocksource timer.
   8
   9 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  10 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
  11 Link: https://lore.kernel.org/r/1611061165-30180-1-git-send-email-claudiu.beznea@microchip.com
  12 ---
  13  drivers/clocksource/timer-microchip-pit64b.c | 86 ++++++++++++++++----
  14  1 file changed, 71 insertions(+), 15 deletions(-)
  15
  16 --- a/drivers/clocksource/timer-microchip-pit64b.c
  17 +++ b/drivers/clocksource/timer-microchip-pit64b.c
  18 @@ -71,10 +71,24 @@ struct mchp_pit64b_clkevt {
  19         struct clock_event_device       clkevt;
  20  };
  21
  22 -#define to_mchp_pit64b_timer(x) \
  23 +#define clkevt_to_mchp_pit64b_timer(x) \
  24         ((struct mchp_pit64b_timer *)container_of(x,\
  25                 struct mchp_pit64b_clkevt, clkevt))
  26
  27 +/**
  28 + * mchp_pit64b_clksrc - PIT64B clocksource data structure
  29 + * @timer: PIT64B timer
  30 + * @clksrc: clocksource
  31 + */
  32 +struct mchp_pit64b_clksrc {
  33 +       struct mchp_pit64b_timer        timer;
  34 +       struct clocksource              clksrc;
  35 +};
  36 +
  37 +#define clksrc_to_mchp_pit64b_timer(x) \
  38 +       ((struct mchp_pit64b_timer *)container_of(x,\
  39 +               struct mchp_pit64b_clksrc, clksrc))
  40 +
  41  /* Base address for clocksource timer. */
  42  static void __iomem *mchp_pit64b_cs_base;
  43  /* Default cycles for clockevent timer. */
  44 @@ -116,6 +130,36 @@ static inline void mchp_pit64b_reset(str
  45         writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
  46  }
  47
  48 +static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)
  49 +{
  50 +       writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
  51 +       if (timer->mode & MCHP_PIT64B_MR_SGCLK)
  52 +               clk_disable_unprepare(timer->gclk);
  53 +       clk_disable_unprepare(timer->pclk);
  54 +}
  55 +
  56 +static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)
  57 +{
  58 +       clk_prepare_enable(timer->pclk);
  59 +       if (timer->mode & MCHP_PIT64B_MR_SGCLK)
  60 +               clk_prepare_enable(timer->gclk);
  61 +}
  62 +
  63 +static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)
  64 +{
  65 +       struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
  66 +
  67 +       mchp_pit64b_suspend(timer);
  68 +}
  69 +
  70 +static void mchp_pit64b_clksrc_resume(struct clocksource *cs)
  71 +{
  72 +       struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
  73 +
  74 +       mchp_pit64b_resume(timer);
  75 +       mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
  76 +}
  77 +
  78  static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
  79  {
  80         return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
  81 @@ -128,7 +172,7 @@ static u64 notrace mchp_pit64b_sched_rea
  82
  83  static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
  84  {
  85 -       struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
  86 +       struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
  87
  88         writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
  89
  90 @@ -137,7 +181,7 @@ static int mchp_pit64b_clkevt_shutdown(s
  91
  92  static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
  93  {
  94 -       struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
  95 +       struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
  96
  97         mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
  98                           MCHP_PIT64B_IER_PERIOD);
  99 @@ -148,7 +192,7 @@ static int mchp_pit64b_clkevt_set_period
 100  static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
 101                                              struct clock_event_device *cedev)
 102  {
 103 -       struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
 104 +       struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
 105
 106         mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
 107                           MCHP_PIT64B_IER_PERIOD);
 108 @@ -158,21 +202,16 @@ static int mchp_pit64b_clkevt_set_next_e
 109
 110  static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
 111  {
 112 -       struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
 113 +       struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
 114
 115 -       writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
 116 -       if (timer->mode & MCHP_PIT64B_MR_SGCLK)
 117 -               clk_disable_unprepare(timer->gclk);
 118 -       clk_disable_unprepare(timer->pclk);
 119 +       mchp_pit64b_suspend(timer);
 120  }
 121
 122  static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
 123  {
 124 -       struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
 125 +       struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
 126
 127 -       clk_prepare_enable(timer->pclk);
 128 -       if (timer->mode & MCHP_PIT64B_MR_SGCLK)
 129 -               clk_prepare_enable(timer->gclk);
 130 +       mchp_pit64b_resume(timer);
 131  }
 132
 133  static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
 134 @@ -296,20 +335,37 @@ done:
 135  static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
 136                                           u32 clk_rate)
 137  {
 138 +       struct mchp_pit64b_clksrc *cs;
 139         int ret;
 140
 141 +       cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 142 +       if (!cs)
 143 +               return -ENOMEM;
 144 +
 145         mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
 146
 147         mchp_pit64b_cs_base = timer->base;
 148
 149 -       ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate,
 150 -                                   210, 64, mchp_pit64b_clksrc_read);
 151 +       cs->timer.base = timer->base;
 152 +       cs->timer.pclk = timer->pclk;
 153 +       cs->timer.gclk = timer->gclk;
 154 +       cs->timer.mode = timer->mode;
 155 +       cs->clksrc.name = MCHP_PIT64B_NAME;
 156 +       cs->clksrc.mask = CLOCKSOURCE_MASK(64);
 157 +       cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 158 +       cs->clksrc.rating = 210;
 159 +       cs->clksrc.read = mchp_pit64b_clksrc_read;
 160 +       cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;
 161 +       cs->clksrc.resume = mchp_pit64b_clksrc_resume;
 162 +
 163 +       ret = clocksource_register_hz(&cs->clksrc, clk_rate);
 164         if (ret) {
 165                 pr_debug("clksrc: Failed to register PIT64B clocksource!\n");
 166
 167                 /* Stop timer. */
 168                 writel_relaxed(MCHP_PIT64B_CR_SWRST,
 169                                timer->base + MCHP_PIT64B_CR);
 170 +               kfree(cs);
 171
 172                 return ret;
 173         }