target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch

   1 From 4833d6ea13a6d2c44a91247991a82c3eb6c1613e Mon Sep 17 00:00:00 2001
   2 From: Eugen Hristev <eugen.hristev@microchip.com>
   3 Date: Fri, 16 Oct 2020 12:39:18 +0300
   4 Subject: [PATCH 134/247] dmaengine: at_xdmac: add AXI priority support and
   5  recommended settings
   6
   7 The sama7g5 version of the XDMAC supports priority configuration and
   8 outstanding capabilities.
   9 Add defines for the specific registers for this configuration, together
  10 with recommended settings.
  11 However the settings are very different if the XDMAC is a mem2mem or a
  12 per2mem controller.
  13 Thus, we need to differentiate according to device tree property.
  14
  15 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
  16 Link: https://lore.kernel.org/r/20201016093918.290137-1-eugen.hristev@microchip.com
  17 Signed-off-by: Vinod Koul <vkoul@kernel.org>
  18 ---
  19  drivers/dma/at_xdmac.c | 47 ++++++++++++++++++++++++++++++++++++++++++
  20  1 file changed, 47 insertions(+)
  21
  22 --- a/drivers/dma/at_xdmac.c
  23 +++ b/drivers/dma/at_xdmac.c
  24 @@ -30,7 +30,24 @@
  25  #define                AT_XDMAC_FIFO_SZ(i)     (((i) >> 5) & 0x7FF)            /* Number of Bytes */
  26  #define                AT_XDMAC_NB_REQ(i)      ((((i) >> 16) & 0x3F) + 1)      /* Number of Peripheral Requests Minus One */
  27  #define AT_XDMAC_GCFG          0x04    /* Global Configuration Register */
  28 +#define                AT_XDMAC_WRHP(i)                (((i) & 0xF) << 4)
  29 +#define                AT_XDMAC_WRMP(i)                (((i) & 0xF) << 8)
  30 +#define                AT_XDMAC_WRLP(i)                (((i) & 0xF) << 12)
  31 +#define                AT_XDMAC_RDHP(i)                (((i) & 0xF) << 16)
  32 +#define                AT_XDMAC_RDMP(i)                (((i) & 0xF) << 20)
  33 +#define                AT_XDMAC_RDLP(i)                (((i) & 0xF) << 24)
  34 +#define                AT_XDMAC_RDSG(i)                (((i) & 0xF) << 28)
  35 +#define AT_XDMAC_GCFG_M2M      (AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF))
  36 +#define AT_XDMAC_GCFG_P2M      (AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \
  37 +                               AT_XDMAC_WRHP(0x5))
  38  #define AT_XDMAC_GWAC          0x08    /* Global Weighted Arbiter Configuration Register */
  39 +#define                AT_XDMAC_PW0(i)         (((i) & 0xF) << 0)
  40 +#define                AT_XDMAC_PW1(i)         (((i) & 0xF) << 4)
  41 +#define                AT_XDMAC_PW2(i)         (((i) & 0xF) << 8)
  42 +#define                AT_XDMAC_PW3(i)         (((i) & 0xF) << 12)
  43 +#define AT_XDMAC_GWAC_M2M      0
  44 +#define AT_XDMAC_GWAC_P2M      (AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF))
  45 +
  46  #define AT_XDMAC_GIE           0x0C    /* Global Interrupt Enable Register */
  47  #define AT_XDMAC_GID           0x10    /* Global Interrupt Disable Register */
  48  #define AT_XDMAC_GIM           0x14    /* Global Interrupt Mask Register */
  49 @@ -190,6 +207,8 @@ struct at_xdmac_layout {
  50         u8                              chan_cc_reg_base;
  51         /* Source/Destination Interface must be specified or not */
  52         bool                            sdif;
  53 +       /* AXI queue priority configuration supported */
  54 +       bool                            axi_config;
  55  };
  56
  57  /* ----- Channels ----- */
  58 @@ -268,6 +287,7 @@ static const struct at_xdmac_layout at_x
  59         .gswf = 0x40,
  60         .chan_cc_reg_base = 0x50,
  61         .sdif = true,
  62 +       .axi_config = false,
  63  };
  64
  65  static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
  66 @@ -280,6 +300,7 @@ static const struct at_xdmac_layout at_x
  67         .gswf = 0x50,
  68         .chan_cc_reg_base = 0x60,
  69         .sdif = false,
  70 +       .axi_config = true,
  71  };
  72
  73  static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
  74 @@ -2003,6 +2024,30 @@ static int atmel_xdmac_resume(struct dev
  75  }
  76  #endif /* CONFIG_PM_SLEEP */
  77
  78 +static void at_xdmac_axi_config(struct platform_device *pdev)
  79 +{
  80 +       struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
  81 +       bool dev_m2m = false;
  82 +       u32 dma_requests;
  83 +
  84 +       if (!atxdmac->layout->axi_config)
  85 +               return; /* Not supported */
  86 +
  87 +       if (!of_property_read_u32(pdev->dev.of_node, "dma-requests",
  88 +                                 &dma_requests)) {
  89 +               dev_info(&pdev->dev, "controller in mem2mem mode.\n");
  90 +               dev_m2m = true;
  91 +       }
  92 +
  93 +       if (dev_m2m) {
  94 +               at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);
  95 +               at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);
  96 +       } else {
  97 +               at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);
  98 +               at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);
  99 +       }
 100 +}
 101 +
 102  static int at_xdmac_probe(struct platform_device *pdev)
 103  {
 104         struct at_xdmac *atxdmac;
 105 @@ -2147,6 +2192,8 @@ static int at_xdmac_probe(struct platfor
 106         dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
 107                  nr_channels, atxdmac->regs);
 108
 109 +       at_xdmac_axi_config(pdev);
 110 +
 111         return 0;
 112
 113  err_dma_unregister: