target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c

   1 /*
   2  * SPI controller driver for the Mikrotik RB4xx boards
   3  *
   4  * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * This file was based on the patches for Linux 2.6.27.39 published by
   7  * MikroTik for their RouterBoard 4xx series devices.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/delay.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/spi/spi.h>
  25
  26 #include <asm/mach-ath79/ar71xx_regs.h>
  27 #include <asm/mach-ath79/ath79.h>
  28
  29 #define DRV_NAME        "rb4xx-spi"
  30 #define DRV_DESC        "Mikrotik RB4xx SPI controller driver"
  31 #define DRV_VERSION     "0.1.0"
  32
  33 #define SPI_CTRL_FASTEST        0x40
  34 #define SPI_FLASH_HZ            33333334
  35 #define SPI_CPLD_HZ             33333334
  36
  37 #define CPLD_CMD_READ_FAST      0x0b
  38
  39 #undef RB4XX_SPI_DEBUG
  40
  41 struct rb4xx_spi {
  42         void __iomem            *base;
  43         struct spi_master       *master;
  44
  45         unsigned                spi_ctrl_flash;
  46         unsigned                spi_ctrl_fread;
  47
  48         struct clk              *ahb_clk;
  49         unsigned long           ahb_freq;
  50
  51         spinlock_t              lock;
  52         struct list_head        queue;
  53         int                     busy:1;
  54         int                     cs_wait;
  55 };
  56
  57 static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1;
  58
  59 #ifdef RB4XX_SPI_DEBUG
  60 static inline void do_spi_delay(void)
  61 {
  62         ndelay(20000);
  63 }
  64 #else
  65 static inline void do_spi_delay(void) { }
  66 #endif
  67
  68 static inline void do_spi_init(struct spi_device *spi)
  69 {
  70         unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1;
  71
  72         if (!(spi->mode & SPI_CS_HIGH))
  73                 cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 :
  74                                                 AR71XX_SPI_IOC_CS0;
  75
  76         spi_clk_low = cs;
  77 }
  78
  79 static inline void do_spi_finish(void __iomem *base)
  80 {
  81         do_spi_delay();
  82         __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1,
  83                      base + AR71XX_SPI_REG_IOC);
  84 }
  85
  86 static inline void do_spi_clk(void __iomem *base, int bit)
  87 {
  88         unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0);
  89
  90         do_spi_delay();
  91         __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
  92         do_spi_delay();
  93         __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
  94 }
  95
  96 static void do_spi_byte(void __iomem *base, unsigned char byte)
  97 {
  98         do_spi_clk(base, byte >> 7);
  99         do_spi_clk(base, byte >> 6);
 100         do_spi_clk(base, byte >> 5);
 101         do_spi_clk(base, byte >> 4);
 102         do_spi_clk(base, byte >> 3);
 103         do_spi_clk(base, byte >> 2);
 104         do_spi_clk(base, byte >> 1);
 105         do_spi_clk(base, byte);
 106
 107         pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
 108                (unsigned)byte,
 109                (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS));
 110 }
 111
 112 static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
 113                                    unsigned bit2)
 114 {
 115         unsigned bval = (spi_clk_low |
 116                          ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) |
 117                          ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0));
 118         do_spi_delay();
 119         __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
 120         do_spi_delay();
 121         __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
 122 }
 123
 124 static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
 125 {
 126         do_spi_clk_fast(base, byte >> 7, byte >> 6);
 127         do_spi_clk_fast(base, byte >> 5, byte >> 4);
 128         do_spi_clk_fast(base, byte >> 3, byte >> 2);
 129         do_spi_clk_fast(base, byte >> 1, byte >> 0);
 130
 131         pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
 132                (unsigned)byte,
 133                (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS));
 134 }
 135
 136 static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
 137 {
 138         const unsigned char *tx_ptr = t->tx_buf;
 139         unsigned char *rx_ptr = t->rx_buf;
 140         unsigned i;
 141
 142         pr_debug("spi_txrx len %u tx %u rx %u\n",
 143                t->len,
 144                (t->tx_buf ? 1 : 0),
 145                (t->rx_buf ? 1 : 0));
 146
 147         for (i = 0; i < t->len; ++i) {
 148                 unsigned char sdata = tx_ptr ? tx_ptr[i] : 0;
 149
 150                 if (t->tx_nbits == SPI_NBITS_DUAL)
 151                         do_spi_byte_fast(base, sdata);
 152                 else
 153                         do_spi_byte(base, sdata);
 154
 155                 if (rx_ptr)
 156                         rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff;
 157         }
 158
 159         return i;
 160 }
 161
 162 static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m)
 163 {
 164         struct spi_transfer *t = NULL;
 165         void __iomem *base = rbspi->base;
 166
 167         m->status = 0;
 168         if (list_empty(&m->transfers))
 169                 return -1;
 170
 171         __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
 172         __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL);
 173         do_spi_init(m->spi);
 174
 175         list_for_each_entry(t, &m->transfers, transfer_list) {
 176                 int len;
 177
 178                 len = rb4xx_spi_txrx(base, t);
 179                 if (len != t->len) {
 180                         m->status = -EMSGSIZE;
 181                         break;
 182                 }
 183                 m->actual_length += len;
 184
 185                 if (t->cs_change) {
 186                         if (list_is_last(&t->transfer_list, &m->transfers)) {
 187                                 /* wait for continuation */
 188                                 return m->spi->chip_select;
 189                         }
 190                         do_spi_finish(base);
 191                         ndelay(100);
 192                 }
 193         }
 194
 195         do_spi_finish(base);
 196         __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
 197         __raw_writel(0, base + AR71XX_SPI_REG_FS);
 198         return -1;
 199 }
 200
 201 static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi,
 202                                            unsigned long *flags)
 203 {
 204         int cs = rbspi->cs_wait;
 205
 206         rbspi->busy = 1;
 207         while (!list_empty(&rbspi->queue)) {
 208                 struct spi_message *m;
 209
 210                 list_for_each_entry(m, &rbspi->queue, queue)
 211                         if (cs < 0 || cs == m->spi->chip_select)
 212                                 break;
 213
 214                 if (&m->queue == &rbspi->queue)
 215                         break;
 216
 217                 list_del_init(&m->queue);
 218                 spin_unlock_irqrestore(&rbspi->lock, *flags);
 219
 220                 cs = rb4xx_spi_msg(rbspi, m);
 221                 m->complete(m->context);
 222
 223                 spin_lock_irqsave(&rbspi->lock, *flags);
 224         }
 225
 226         rbspi->cs_wait = cs;
 227         rbspi->busy = 0;
 228
 229         if (cs >= 0) {
 230                 /* TODO: add timer to unlock cs after 1s inactivity */
 231         }
 232 }
 233
 234 static int rb4xx_spi_transfer(struct spi_device *spi,
 235                               struct spi_message *m)
 236 {
 237         struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
 238         unsigned long flags;
 239
 240         m->actual_length = 0;
 241         m->status = -EINPROGRESS;
 242
 243         spin_lock_irqsave(&rbspi->lock, flags);
 244         list_add_tail(&m->queue, &rbspi->queue);
 245         if (rbspi->busy ||
 246             (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) {
 247                 /* job will be done later */
 248                 spin_unlock_irqrestore(&rbspi->lock, flags);
 249                 return 0;
 250         }
 251
 252         /* process job in current context */
 253         rb4xx_spi_process_queue_locked(rbspi, &flags);
 254         spin_unlock_irqrestore(&rbspi->lock, flags);
 255
 256         return 0;
 257 }
 258
 259 static int rb4xx_spi_setup(struct spi_device *spi)
 260 {
 261         struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
 262         unsigned long flags;
 263
 264         if (spi->mode & ~(SPI_CS_HIGH | SPI_TX_DUAL)) {
 265                 dev_err(&spi->dev, "mode %x not supported\n",
 266                         (unsigned) spi->mode);
 267                 return -EINVAL;
 268         }
 269
 270         if (spi->bits_per_word != 8 && spi->bits_per_word != 0) {
 271                 dev_err(&spi->dev, "bits_per_word %u not supported\n",
 272                         (unsigned) spi->bits_per_word);
 273                 return -EINVAL;
 274         }
 275
 276         spin_lock_irqsave(&rbspi->lock, flags);
 277         if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) {
 278                 rbspi->cs_wait = -1;
 279                 rb4xx_spi_process_queue_locked(rbspi, &flags);
 280         }
 281         spin_unlock_irqrestore(&rbspi->lock, flags);
 282
 283         return 0;
 284 }
 285
 286 static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max,
 287                              const char *name)
 288 {
 289         unsigned div;
 290
 291         div = (rbspi->ahb_freq - 1) / (2 * hz_max);
 292
 293         /*
 294          * CPU has a bug at (div == 0) - first bit read is random
 295          */
 296         if (div == 0)
 297                 ++div;
 298
 299         if (name) {
 300                 unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000;
 301                 unsigned div_real = 2 * (div + 1);
 302                 pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
 303                        name,
 304                        ahb_khz / div_real,
 305                        ahb_khz, div_real);
 306         }
 307
 308         return SPI_CTRL_FASTEST + div;
 309 }
 310
 311 static int rb4xx_spi_probe(struct platform_device *pdev)
 312 {
 313         struct spi_master *master;
 314         struct rb4xx_spi *rbspi;
 315         struct resource *r;
 316         int err = 0;
 317
 318         master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
 319         if (master == NULL) {
 320                 dev_err(&pdev->dev, "no memory for spi_master\n");
 321                 err = -ENOMEM;
 322                 goto err_out;
 323         }
 324
 325         master->bus_num = 0;
 326         master->num_chipselect = 3;
 327         master->mode_bits = SPI_TX_DUAL;
 328         master->setup = rb4xx_spi_setup;
 329         master->transfer = rb4xx_spi_transfer;
 330
 331         rbspi = spi_master_get_devdata(master);
 332
 333         rbspi->ahb_clk = clk_get(&pdev->dev, "ahb");
 334         if (IS_ERR(rbspi->ahb_clk)) {
 335                 err = PTR_ERR(rbspi->ahb_clk);
 336                 goto err_put_master;
 337         }
 338
 339         err = clk_prepare_enable(rbspi->ahb_clk);
 340         if (err)
 341                 goto err_clk_put;
 342
 343         rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk);
 344         if (!rbspi->ahb_freq) {
 345                 err = -EINVAL;
 346                 goto err_clk_disable;
 347         }
 348
 349         platform_set_drvdata(pdev, rbspi);
 350
 351         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 352         if (r == NULL) {
 353                 err = -ENOENT;
 354                 goto err_clk_disable;
 355         }
 356
 357         rbspi->base = ioremap(r->start, r->end - r->start + 1);
 358         if (!rbspi->base) {
 359                 err = -ENXIO;
 360                 goto err_clk_disable;
 361         }
 362
 363         rbspi->master = master;
 364         rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH");
 365         rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD");
 366         rbspi->cs_wait = -1;
 367
 368         spin_lock_init(&rbspi->lock);
 369         INIT_LIST_HEAD(&rbspi->queue);
 370
 371         err = spi_register_master(master);
 372         if (err) {
 373                 dev_err(&pdev->dev, "failed to register SPI master\n");
 374                 goto err_iounmap;
 375         }
 376
 377         return 0;
 378
 379 err_iounmap:
 380         iounmap(rbspi->base);
 381 err_clk_disable:
 382         clk_disable(rbspi->ahb_clk);
 383 err_clk_put:
 384         clk_put(rbspi->ahb_clk);
 385 err_put_master:
 386         platform_set_drvdata(pdev, NULL);
 387         spi_master_put(master);
 388 err_out:
 389         return err;
 390 }
 391
 392 static int rb4xx_spi_remove(struct platform_device *pdev)
 393 {
 394         struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
 395
 396         iounmap(rbspi->base);
 397         clk_disable(rbspi->ahb_clk);
 398         clk_put(rbspi->ahb_clk);
 399         platform_set_drvdata(pdev, NULL);
 400         spi_master_put(rbspi->master);
 401
 402         return 0;
 403 }
 404
 405 static struct platform_driver rb4xx_spi_drv = {
 406         .probe          = rb4xx_spi_probe,
 407         .remove         = rb4xx_spi_remove,
 408         .driver         = {
 409                 .name   = DRV_NAME,
 410                 .owner  = THIS_MODULE,
 411         },
 412 };
 413
 414 static int __init rb4xx_spi_init(void)
 415 {
 416         return platform_driver_register(&rb4xx_spi_drv);
 417 }
 418 subsys_initcall(rb4xx_spi_init);
 419
 420 static void __exit rb4xx_spi_exit(void)
 421 {
 422         platform_driver_unregister(&rb4xx_spi_drv);
 423 }
 424
 425 module_exit(rb4xx_spi_exit);
 426
 427 MODULE_DESCRIPTION(DRV_DESC);
 428 MODULE_VERSION(DRV_VERSION);
 429 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 430 MODULE_LICENSE("GPL v2");