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ar71xx: add support for MikroTik hAP ac lite
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-rbspi.c
1 /*
2 * MikroTik SPI-NOR RouterBOARDs support
3 *
4 * - MikroTik RouterBOARD mAP L-2nD
5 * - MikroTik RouterBOARD 941L-2nD
6 * - MikroTik RouterBOARD 951Ui-2nD
7 * - MikroTik RouterBOARD 952Ui-5ac2nD
8 * - MikroTik RouterBOARD 750UP r2
9 * - MikroTik RouterBOARD 750 r2
10 * - MikroTik RouterBOARD LHG 5nD
11 *
12 * Preliminary support for the following hardware
13 * - MikroTik RouterBOARD wAP2nD
14 * - MikroTik RouterBOARD cAP2nD
15 * - MikroTik RouterBOARD mAP2nD
16 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
17 * hardware as the mAP L-2nD. It is unknown if they share the same board
18 * identifier.
19 *
20 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License version 2 as published
24 * by the Free Software Foundation.
25 */
26
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
30 #include <linux/routerboot.h>
31 #include <linux/gpio.h>
32
33 #include <linux/spi/spi.h>
34 #include <linux/spi/74x164.h>
35
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/partitions.h>
38
39 #include <asm/prom.h>
40 #include <asm/mach-ath79/ar71xx_regs.h>
41 #include <asm/mach-ath79/ath79.h>
42
43 #include "common.h"
44 #include "dev-eth.h"
45 #include "dev-spi.h"
46 #include "dev-gpio-buttons.h"
47 #include "dev-leds-gpio.h"
48 #include "dev-m25p80.h"
49 #include "dev-usb.h"
50 #include "dev-wmac.h"
51 #include "machtypes.h"
52 #include "pci.h"
53 #include "routerboot.h"
54
55 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
56 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
57
58 #define RBSPI_HAS_USB BIT(0)
59 #define RBSPI_HAS_WLAN0 BIT(1)
60 #define RBSPI_HAS_WLAN1 BIT(2)
61 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
62 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
63 #define RBSPI_HAS_POE BIT(5)
64 #define RBSPI_HAS_MDIO1 BIT(6)
65 #define RBSPI_HAS_PCI BIT(7)
66
67 #define RB_ROUTERBOOT_OFFSET 0x0000
68 #define RB_BIOS_SIZE 0x1000
69 #define RB_SOFT_CFG_SIZE 0x1000
70
71 /* Flash partitions indexes */
72 enum {
73 RBSPI_PART_RBOOT,
74 RBSPI_PART_HCONF,
75 RBSPI_PART_BIOS,
76 RBSPI_PART_RBOOT2,
77 RBSPI_PART_SCONF,
78 RBSPI_PART_FIRMW,
79 RBSPI_PARTS
80 };
81
82 static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
83
84 /*
85 * Setup the SPI flash partition table based on initial parsing.
86 * The kernel can be at any aligned position and have any size.
87 */
88 static void __init rbspi_init_partitions(const struct rb_info *info)
89 {
90 struct mtd_partition *parts = rbspi_spi_partitions;
91 memset(parts, 0x0, sizeof(*parts));
92
93 parts[RBSPI_PART_RBOOT].name = "routerboot";
94 parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
95 parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
96 parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
97
98 parts[RBSPI_PART_HCONF].name = "hard_config";
99 parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
100 parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
101 parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
102
103 parts[RBSPI_PART_BIOS].name = "bios";
104 parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
105 + info->hard_cfg_size;
106 parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
107 parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
108
109 parts[RBSPI_PART_RBOOT2].name = "routerboot2";
110 parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
111 + RB_BIOS_SIZE;
112 parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
113 - parts[RBSPI_PART_RBOOT2].offset;
114 parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
115
116 parts[RBSPI_PART_SCONF].name = "soft_config";
117 parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
118 parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
119
120 parts[RBSPI_PART_FIRMW].name = "firmware";
121 parts[RBSPI_PART_FIRMW].offset = parts[RBSPI_PART_SCONF].offset
122 + parts[RBSPI_PART_SCONF].size;
123 parts[RBSPI_PART_FIRMW].size = MTDPART_SIZ_FULL;
124 }
125
126 static struct flash_platform_data rbspi_spi_flash_data = {
127 .parts = rbspi_spi_partitions,
128 .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
129 };
130
131 /* Several boards only have a single reset button wired to GPIO 16 */
132 #define RBSPI_GPIO_BTN_RESET16 16
133
134 static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
135 {
136 .desc = "Reset button",
137 .type = EV_KEY,
138 .code = KEY_RESTART,
139 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
140 .gpio = RBSPI_GPIO_BTN_RESET16,
141 .active_low = 1,
142 },
143 };
144
145 /* RB mAP L-2nD gpios */
146 #define RBMAPL_GPIO_LED_POWER 17
147 #define RBMAPL_GPIO_LED_USER 14
148 #define RBMAPL_GPIO_LED_ETH 4
149 #define RBMAPL_GPIO_LED_WLAN 11
150
151 static struct gpio_led rbmapl_leds[] __initdata = {
152 {
153 .name = "rb:green:power",
154 .gpio = RBMAPL_GPIO_LED_POWER,
155 .active_low = 0,
156 .default_state = LEDS_GPIO_DEFSTATE_ON,
157 }, {
158 .name = "rb:green:user",
159 .gpio = RBMAPL_GPIO_LED_USER,
160 .active_low = 0,
161 }, {
162 .name = "rb:green:eth",
163 .gpio = RBMAPL_GPIO_LED_ETH,
164 .active_low = 0,
165 }, {
166 .name = "rb:green:wlan",
167 .gpio = RBMAPL_GPIO_LED_WLAN,
168 .active_low = 0,
169 },
170 };
171
172 /* RB 941L-2nD gpios */
173 #define RBHAPL_GPIO_LED_USER 14
174 static struct gpio_led rbhapl_leds[] __initdata = {
175 {
176 .name = "rb:green:user",
177 .gpio = RBHAPL_GPIO_LED_USER,
178 .active_low = 1,
179 },
180 };
181
182 /* common RB SSRs */
183 #define RBSPI_SSR_GPIO_BASE 40
184 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
185
186 /* RB 951Ui-2nD gpios */
187 #define RB952_SSR_BIT_LED_LAN1 0
188 #define RB952_SSR_BIT_LED_LAN2 1
189 #define RB952_SSR_BIT_LED_LAN3 2
190 #define RB952_SSR_BIT_LED_LAN4 3
191 #define RB952_SSR_BIT_LED_LAN5 4
192 #define RB952_SSR_BIT_USB_POWER 5
193 #define RB952_SSR_BIT_LED_WLAN 6
194 #define RB952_GPIO_SSR_CS 11
195 #define RB952_GPIO_LED_USER 4
196 #define RB952_GPIO_POE_POWER 14
197 #define RB952_GPIO_POE_STATUS 12
198 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
199 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
200 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
201 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
202 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
203 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
204 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
205
206 static struct gpio_led rb952_leds[] __initdata = {
207 {
208 .name = "rb:green:user",
209 .gpio = RB952_GPIO_LED_USER,
210 .active_low = 0,
211 }, {
212 .name = "rb:blue:wlan",
213 .gpio = RB952_GPIO_LED_WLAN,
214 .active_low = 1,
215 }, {
216 .name = "rb:green:port1",
217 .gpio = RB952_GPIO_LED_LAN1,
218 .active_low = 1,
219 }, {
220 .name = "rb:green:port2",
221 .gpio = RB952_GPIO_LED_LAN2,
222 .active_low = 1,
223 }, {
224 .name = "rb:green:port3",
225 .gpio = RB952_GPIO_LED_LAN3,
226 .active_low = 1,
227 }, {
228 .name = "rb:green:port4",
229 .gpio = RB952_GPIO_LED_LAN4,
230 .active_low = 1,
231 }, {
232 .name = "rb:green:port5",
233 .gpio = RB952_GPIO_LED_LAN5,
234 .active_low = 1,
235 },
236 };
237
238 /* RB wAP-2nD gpios */
239 #define RBWAP_GPIO_LED_USER 14
240 #define RBWAP_GPIO_LED_WLAN 11
241
242 static struct gpio_led rbwap_leds[] __initdata = {
243 {
244 .name = "rb:green:user",
245 .gpio = RBWAP_GPIO_LED_USER,
246 .active_low = 1,
247 }, {
248 .name = "rb:green:wlan",
249 .gpio = RBWAP_GPIO_LED_WLAN,
250 .active_low = 1,
251 },
252 };
253
254 /* RB cAP-2nD gpios */
255 #define RBCAP_GPIO_LED_1 14
256 #define RBCAP_GPIO_LED_2 12
257 #define RBCAP_GPIO_LED_3 11
258 #define RBCAP_GPIO_LED_4 4
259 #define RBCAP_GPIO_LED_ALL 13
260
261 static struct gpio_led rbcap_leds[] __initdata = {
262 {
263 .name = "rb:green:rssi1",
264 .gpio = RBCAP_GPIO_LED_1,
265 .active_low = 1,
266 }, {
267 .name = "rb:green:rssi2",
268 .gpio = RBCAP_GPIO_LED_2,
269 .active_low = 1,
270 }, {
271 .name = "rb:green:rssi3",
272 .gpio = RBCAP_GPIO_LED_3,
273 .active_low = 1,
274 }, {
275 .name = "rb:green:rssi4",
276 .gpio = RBCAP_GPIO_LED_4,
277 .active_low = 1,
278 },
279 };
280
281 /* RB mAP-2nD gpios */
282 #define RBMAP_SSR_BIT_LED_LAN1 0
283 #define RBMAP_SSR_BIT_LED_LAN2 1
284 #define RBMAP_SSR_BIT_LED_POEO 2
285 #define RBMAP_SSR_BIT_LED_USER 3
286 #define RBMAP_SSR_BIT_LED_WLAN 4
287 #define RBMAP_SSR_BIT_USB_POWER 5
288 #define RBMAP_SSR_BIT_LED_APCAP 6
289 #define RBMAP_GPIO_SSR_CS 11
290 #define RBMAP_GPIO_LED_POWER 4
291 #define RBMAP_GPIO_POE_POWER 14
292 #define RBMAP_GPIO_POE_STATUS 12
293 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
294 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
295 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
296 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
297 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
298 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
299 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
300
301 static struct gpio_led rbmap_leds[] __initdata = {
302 {
303 .name = "rb:green:power",
304 .gpio = RBMAP_GPIO_LED_POWER,
305 .active_low = 1,
306 .default_state = LEDS_GPIO_DEFSTATE_ON,
307 }, {
308 .name = "rb:green:eth1",
309 .gpio = RBMAP_GPIO_LED_LAN1,
310 .active_low = 1,
311 }, {
312 .name = "rb:green:eth2",
313 .gpio = RBMAP_GPIO_LED_WLAN,
314 .active_low = 1,
315 }, {
316 .name = "rb:red:poe_out",
317 .gpio = RBMAP_GPIO_LED_POEO,
318 .active_low = 1,
319 }, {
320 .name = "rb:green:user",
321 .gpio = RBMAP_GPIO_LED_USER,
322 .active_low = 1,
323 }, {
324 .name = "rb:green:wlan",
325 .gpio = RBMAP_GPIO_LED_WLAN,
326 .active_low = 1,
327 }, {
328 .name = "rb:green:ap_cap",
329 .gpio = RBMAP_GPIO_LED_APCAP,
330 .active_low = 1,
331 },
332 };
333
334 /* RB LHG 5nD gpios */
335 #define RBLHG_GPIO_LED_0 13
336 #define RBLHG_GPIO_LED_1 12
337 #define RBLHG_GPIO_LED_2 4
338 #define RBLHG_GPIO_LED_3 21
339 #define RBLHG_GPIO_LED_4 18
340 #define RBLHG_GPIO_LED_ETH 14
341 #define RBLHG_GPIO_LED_POWER 11
342 #define RBLHG_GPIO_LED_USER 20
343 #define RBLHG_GPIO_BTN_RESET 15
344
345 static struct gpio_led rblhg_leds[] __initdata = {
346 {
347 .name = "rb:green:rssi0",
348 .gpio = RBLHG_GPIO_LED_0,
349 .active_low = 1,
350 }, {
351 .name = "rb:green:rssi1",
352 .gpio = RBLHG_GPIO_LED_1,
353 .active_low = 1,
354 }, {
355 .name = "rb:green:rssi2",
356 .gpio = RBLHG_GPIO_LED_2,
357 .active_low = 1,
358 }, {
359 .name = "rb:green:rssi3",
360 .gpio = RBLHG_GPIO_LED_3,
361 .active_low = 1,
362 }, {
363 .name = "rb:green:rssi4",
364 .gpio = RBLHG_GPIO_LED_4,
365 .active_low = 1,
366 }, {
367 .name = "rb:green:eth",
368 .gpio = RBLHG_GPIO_LED_ETH,
369 .active_low = 1,
370 }, {
371 .name = "rb:green:user",
372 .gpio = RBLHG_GPIO_LED_USER,
373 .active_low = 1,
374 }, {
375 .name = "rb:blue:power",
376 .gpio = RBLHG_GPIO_LED_POWER,
377 .active_low = 0,
378 .default_state = LEDS_GPIO_DEFSTATE_ON,
379 },
380 };
381
382 static struct gpio_keys_button rblhg_gpio_keys[] __initdata = {
383 {
384 .desc = "Reset button",
385 .type = EV_KEY,
386 .code = KEY_RESTART,
387 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
388 .gpio = RBLHG_GPIO_BTN_RESET,
389 .active_low = 1,
390 },
391 };
392
393
394 static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
395 .base = RBSPI_SSR_GPIO_BASE,
396 };
397
398 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
399 static int rbspi_spi_cs_gpios[] = {
400 -ENOENT, /* CS0 is always -ENOENT: natively handled */
401 -ENOENT, /* CS1 can be updated by the code as necessary */
402 };
403
404 static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
405 .bus_num = 0,
406 .cs_gpios = rbspi_spi_cs_gpios,
407 };
408
409 /*
410 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
411 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
412 */
413 static struct spi_board_info rbspi_spi_info[] = {
414 {
415 .bus_num = 0,
416 .chip_select = 0,
417 .max_speed_hz = 25000000,
418 .modalias = "m25p80",
419 .platform_data = &rbspi_spi_flash_data,
420 }, {
421 .bus_num = 0,
422 .chip_select = 1,
423 .max_speed_hz = 25000000,
424 .modalias = "74x164",
425 .platform_data = &rbspi_ssr_data,
426 }
427 };
428
429 void __init rbspi_wlan_init(u16 id, int wmac_offset)
430 {
431 char *art_buf;
432 u8 wlan_mac[ETH_ALEN];
433
434 art_buf = rb_get_ext_wlan_data(id);
435 if (!art_buf)
436 return;
437
438 ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
439 ath79_register_wmac(art_buf + 0x1000, wlan_mac);
440
441 kfree(art_buf);
442 }
443
444 #define RBSPI_MACH_BUFLEN 64
445 /*
446 * Common platform init routine for all SPI NOR devices.
447 */
448 static int __init rbspi_platform_setup(void)
449 {
450 const struct rb_info *info;
451 char buf[RBSPI_MACH_BUFLEN] = "MikroTik ";
452 char *str;
453 int len = RBSPI_MACH_BUFLEN - strlen(buf) - 1;
454
455 info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
456 if (!info)
457 return -ENODEV;
458
459 if (info->board_name) {
460 str = "RouterBOARD ";
461 if (strncmp(info->board_name, str, strlen(str))) {
462 strncat(buf, str, len);
463 len -= strlen(str);
464 }
465 strncat(buf, info->board_name, len);
466 }
467 else
468 strncat(buf, "UNKNOWN", len);
469
470 mips_set_machine_name(buf);
471
472 /* fix partitions based on flash parsing */
473 rbspi_init_partitions(info);
474
475 return 0;
476 }
477
478 /*
479 * Common peripherals init routine for all SPI NOR devices.
480 * Sets SPI and USB.
481 */
482 static void __init rbspi_peripherals_setup(u32 flags)
483 {
484 unsigned spi_n;
485
486 if (flags & RBSPI_HAS_SSR)
487 spi_n = ARRAY_SIZE(rbspi_spi_info);
488 else
489 spi_n = 1; /* only one device on bus0 */
490
491 rbspi_ath79_spi_data.num_chipselect = spi_n;
492 rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
493 ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
494
495 if (flags & RBSPI_HAS_USB)
496 ath79_register_usb();
497
498 if (flags & RBSPI_HAS_PCI)
499 ath79_register_pci();
500 }
501
502 /*
503 * Common network init routine for all SPI NOR devices.
504 * Sets LAN/WAN/WLAN.
505 */
506 static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
507 int wmac0_offset, int wmac1_offset)
508 {
509 /* for QCA953x that will init mdio1_device/data */
510 ath79_register_mdio(0, 0x0);
511 if (flags & RBSPI_HAS_MDIO1)
512 ath79_register_mdio(1, 0x0);
513
514 if (flags & RBSPI_HAS_WAN4) {
515 ath79_setup_ar934x_eth_cfg(0);
516
517 /* set switch to oper mode 1, PHY4 connected to CPU */
518 ath79_switch_data.phy4_mii_en = 1;
519 ath79_switch_data.phy_poll_mask |= BIT(4);
520
521 /* init GMAC0 connected to PHY4 at 100M */
522 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
523 ath79_eth0_data.phy_mask = BIT(4);
524 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
525 ath79_register_eth(0);
526 } else {
527 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
528 * to the internal switch.
529 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
530 * the QCA953x, this works because this configuration bit is
531 * the same as the AR934x. There's no equivalent function for
532 * QCA953x for now. */
533 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
534 }
535
536 /* init GMAC1 */
537 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
538 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
539 ath79_register_eth(1);
540
541 if (flags & RBSPI_HAS_WLAN0)
542 rbspi_wlan_init(0, wmac0_offset);
543
544 if (flags & RBSPI_HAS_WLAN1)
545 rbspi_wlan_init(1, wmac1_offset);
546 }
547
548 /*
549 * Init the mAP lite hardware (QCA953x).
550 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
551 * Trying to use GMAC0 in direct mode was unsucessful, so we're
552 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
553 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
554 */
555 static void __init rbmapl_setup(void)
556 {
557 u32 flags = RBSPI_HAS_WLAN0;
558
559 if (rbspi_platform_setup())
560 return;
561
562 rbspi_peripherals_setup(flags);
563
564 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
565 rbspi_network_setup(flags, 0, 1, 0);
566
567 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
568
569 /* mAP lite has a single reset button as gpio 16 */
570 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
571 ARRAY_SIZE(rbspi_gpio_keys_reset16),
572 rbspi_gpio_keys_reset16);
573
574 /* clear internal multiplexing */
575 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
576 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
577 }
578
579 /*
580 * Init the hAP lite hardware (QCA953x).
581 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
582 * being assigned to LAN on the casing, and port 1 being assigned
583 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
584 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
585 */
586 static void __init rbhapl_setup(void)
587 {
588 u32 flags = RBSPI_HAS_WLAN0;
589
590 if (rbspi_platform_setup())
591 return;
592
593 rbspi_peripherals_setup(flags);
594
595 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
596 rbspi_network_setup(flags, 0, 4, 0);
597
598 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds);
599
600 /* hAP lite has a single reset button as gpio 16 */
601 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
602 ARRAY_SIZE(rbspi_gpio_keys_reset16),
603 rbspi_gpio_keys_reset16);
604 }
605
606 /*
607 * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform
608 */
609 static void __init rbspi_952_750r2_setup(u32 flags)
610 {
611 if (flags & RBSPI_HAS_SSR)
612 rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
613
614 rbspi_peripherals_setup(flags);
615
616 /*
617 * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP),
618 * WLAN1 MAC IS HW MAC + 6 (hAP ac lite)
619 */
620 rbspi_network_setup(flags, 1, 5, 6);
621
622 if (flags & RBSPI_HAS_USB)
623 gpio_request_one(RB952_GPIO_USB_POWER,
624 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
625 "USB power");
626
627 if (flags & RBSPI_HAS_POE)
628 gpio_request_one(RB952_GPIO_POE_POWER,
629 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
630 "POE power");
631
632 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
633
634 /* These devices have a single reset button as gpio 16 */
635 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
636 ARRAY_SIZE(rbspi_gpio_keys_reset16),
637 rbspi_gpio_keys_reset16);
638 }
639
640 /*
641 * Init the hAP (ac lite) hardware (QCA953x).
642 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
643 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
644 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
645 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
646 * internal switch for the LAN ports.
647 * The device also has USB, PoE output and an SSR used for LED multiplexing.
648 * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
649 * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
650 */
651 static void __init rb952_setup(void)
652 {
653 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
654 RBSPI_HAS_SSR | RBSPI_HAS_POE;
655
656 if (rbspi_platform_setup())
657 return;
658
659 /* differentiate the hAP from the hAP ac lite */
660 if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
661 flags |= RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI;
662 else
663 flags |= RBSPI_HAS_WLAN0;
664
665 rbspi_952_750r2_setup(flags);
666 }
667
668 /*
669 * Init the hEX (PoE) lite hardware (QCA953x).
670 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
671 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
672 * without USB and POE. It shares the same bootloader board identifier.
673 */
674 static void __init rb750upr2_setup(void)
675 {
676 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR;
677
678 if (rbspi_platform_setup())
679 return;
680
681 /* differentiate the hEX lite from the hEX PoE lite */
682 if (strstr(mips_get_machine_name(), "750UP r2"))
683 flags |= RBSPI_HAS_USB | RBSPI_HAS_POE;
684
685 rbspi_952_750r2_setup(flags);
686 }
687
688 /*
689 * Init the LHG hardware (AR9344).
690 * The LHG 5nD has a single ethernet port connected to PHY0.
691 * Wireless is provided via 5GHz WLAN1.
692 */
693 static void __init rblhg_setup(void)
694 {
695 u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_MDIO1;
696
697 if (rbspi_platform_setup())
698 return;
699
700 rbspi_peripherals_setup(flags);
701
702 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
703 rbspi_network_setup(flags, 0, 0, 1);
704
705 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds), rblhg_leds);
706
707 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
708 ARRAY_SIZE(rblhg_gpio_keys),
709 rblhg_gpio_keys);
710 }
711
712 /*
713 * Init the wAP hardware (EXPERIMENTAL).
714 * The wAP 2nD has a single ethernet port.
715 */
716 static void __init rbwap_setup(void)
717 {
718 u32 flags = RBSPI_HAS_WLAN0;
719
720 if (rbspi_platform_setup())
721 return;
722
723 rbspi_peripherals_setup(flags);
724
725 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
726 rbspi_network_setup(flags, 0, 1, 0);
727
728 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds);
729 }
730
731 /*
732 * Init the cAP hardware (EXPERIMENTAL).
733 * The cAP 2nD has a single ethernet port, and a global LED switch.
734 */
735 static void __init rbcap_setup(void)
736 {
737 u32 flags = RBSPI_HAS_WLAN0;
738
739 if (rbspi_platform_setup())
740 return;
741
742 rbspi_peripherals_setup(flags);
743
744 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
745 rbspi_network_setup(flags, 0, 1, 0);
746
747 gpio_request_one(RBCAP_GPIO_LED_ALL,
748 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
749 "LEDs enable");
750
751 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds), rbcap_leds);
752 }
753
754 /*
755 * Init the mAP hardware (EXPERIMENTAL).
756 * The mAP 2nD has two ethernet ports, PoE output and an SSR for LED
757 * multiplexing.
758 */
759 static void __init rbmap_setup(void)
760 {
761 u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_SSR | RBSPI_HAS_POE;
762
763 if (rbspi_platform_setup())
764 return;
765
766 rbspi_spi_cs_gpios[1] = RBMAP_GPIO_SSR_CS;
767 rbspi_peripherals_setup(flags);
768
769 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
770 rbspi_network_setup(flags, 0, 2, 0);
771
772 if (flags & RBSPI_HAS_POE)
773 gpio_request_one(RBMAP_GPIO_POE_POWER,
774 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
775 "POE power");
776
777 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
778 }
779
780
781 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
782 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
783 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
784 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup);
785 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup);
786 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup);
787 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP, "cap-hb", rbcap_setup);
788 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP, "map2-hb", rbmap_setup);
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