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bd15a8e22a14273c58567ee80c718984385dd796
[openwrt/openwrt.git] / target / linux / apm821xx / dts / apollo3g.dtsi
1 /*
2 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
3 * (c) Copyright 2010 Western Digital Technologies, Inc. All Rights Reserved.
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without
7 * any warranty of any kind, whether express or implied.
8 */
9
10 / {
11 #address-cells = <2>;
12 #size-cells = <1>;
13 compatible = "amcc,apollo3g";
14 dcr-parent = <&{/cpus/cpu@0}>;
15
16 aliases {
17 ethernet0 = &EMAC0;
18 serial0 = &UART0;
19 };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 device_type = "cpu";
27 model = "PowerPC,apm82181";
28 reg = <0x00000000>;
29 clock-frequency = <0>; /* Filled in by U-Boot */
30 timebase-frequency = <0>; /* Filled in by U-Boot */
31 i-cache-line-size = <32>;
32 d-cache-line-size = <32>;
33 i-cache-size = <32768>;
34 d-cache-size = <32768>;
35 dcr-controller;
36 dcr-access-method = "native";
37 next-level-cache = <&L2C0>;
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
44 };
45
46 UIC0: interrupt-controller0 {
47 compatible = "ibm,uic-460ex","ibm,uic";
48 interrupt-controller;
49 cell-index = <0>;
50 dcr-reg = <0x0c0 0x009>;
51 #address-cells = <0>;
52 #size-cells = <0>;
53 #interrupt-cells = <2>;
54 };
55
56 UIC1: interrupt-controller1 {
57 compatible = "ibm,uic-460ex","ibm,uic";
58 interrupt-controller;
59 cell-index = <1>;
60 dcr-reg = <0x0d0 0x009>;
61 #address-cells = <0>;
62 #size-cells = <0>;
63 #interrupt-cells = <2>;
64 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
65 interrupt-parent = <&UIC0>;
66 };
67
68 UIC2: interrupt-controller2 {
69 compatible = "ibm,uic-460ex","ibm,uic";
70 interrupt-controller;
71 cell-index = <2>;
72 dcr-reg = <0x0e0 0x009>;
73 #address-cells = <0>;
74 #size-cells = <0>;
75 #interrupt-cells = <2>;
76 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
77 interrupt-parent = <&UIC0>;
78 };
79
80 UIC3: interrupt-controller3 {
81 compatible = "ibm,uic-460ex","ibm,uic";
82 interrupt-controller;
83 cell-index = <3>;
84 dcr-reg = <0x0f0 0x009>;
85 #address-cells = <0>;
86 #size-cells = <0>;
87 #interrupt-cells = <2>;
88 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
89 interrupt-parent = <&UIC0>;
90 };
91
92 OCM1: ocm@400040000 {
93 compatible = "ibm,ocm";
94 status = "okay";
95 cell-index = <1>;
96 /* configured in U-Boot */
97 reg = <4 0x00040000 0x8000>; /* 32K */
98 };
99
100 SDR0: sdr {
101 compatible = "ibm,sdr-460ex";
102 dcr-reg = <0x00e 0x002>;
103 };
104
105 CPR0: cpr {
106 compatible = "ibm,cpr-460ex";
107 dcr-reg = <0x00c 0x002>;
108 };
109
110 CPM0: cpm {
111 compatible = "ibm,cpm";
112 dcr-access-method = "native";
113 dcr-reg = <0x160 0x003>;
114 unused-units = <0x00000100>;
115 idle-doze = <0x02000000>;
116 standby = <0xfeff791d>;
117 };
118
119 L2C0: l2c {
120 compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
121 dcr-reg = <0x020 0x008
122 0x030 0x008>;
123 cache-line-size = <32>;
124 cache-size = <262144>;
125 interrupt-parent = <&UIC1>;
126 interrupts = <11 1>;
127 };
128
129 plb {
130 compatible = "ibm,plb-460ex", "ibm,plb4";
131 #address-cells = <2>;
132 #size-cells = <1>;
133 ranges;
134 clock-frequency = <0>; /* Filled in by U-Boot */
135
136 SDRAM0: sdram {
137 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
138 dcr-reg = <0x010 0x002>;
139 };
140
141 CRYPTO: crypto@180000 {
142 compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
143 reg = <4 0x00180000 0x80400>;
144 interrupt-parent = <&UIC0>;
145 interrupts = <0x1d 0x4>;
146 };
147
148 PKA: pka@114000 {
149 device_type = "pka";
150 compatible = "ppc4xx-pka", "amcc,ppc4xx-pka";
151 reg = <0 0x00114000 0x4000>;
152 interrupt-parent = <&UIC0>;
153 interrupts = <0x14 0x2>;
154 };
155
156 HWRNG: trng@110000 {
157 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
158 reg = <4 0x00110000 0x50>;
159 };
160
161 MAL0: mcmal {
162 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
163 descriptor-memory = "ocm";
164 dcr-reg = <0x180 0x062>;
165 num-tx-chans = <1>;
166 num-rx-chans = <1>;
167 #address-cells = <0>;
168 #size-cells = <0>;
169 interrupt-parent = <&UIC2>;
170 interrupts = < /*TXEOB*/ 0x6 0x4
171 /*RXEOB*/ 0x7 0x4
172 /*SERR*/ 0x3 0x4
173 /*TXDE*/ 0x4 0x4
174 /*RXDE*/ 0x5 0x4
175 /*TX0 COAL*/ 0x8 0x2
176 /*TX1 COAL 0x9 0x2*/
177 /*RX0 COAL*/ 0xc 0x2
178 /*RX1 COAL 0xd 0x2*/ >;
179 };
180
181 AHBDMA: dma@bffd0800 {
182 compatible = "snps,dma-spear1340";
183 reg = <4 0xbffd0800 0x400>;
184 interrupt-parent = <&UIC0>;
185 interrupts = <25 4>;
186 #dma-cells = <3>;
187 /* use autoconfiguration for the dma setup */
188 };
189
190 SATA0: sata@bffd1000 {
191 compatible = "amcc,sata-460ex";
192 reg = <4 0xbffd1000 0x800>;
193 interrupt-parent = <&UIC0>;
194 interrupts = <26 4>;
195 dmas = <&AHBDMA 0 0 1>;
196 dma-names = "sata-dma";
197 };
198
199 SATA1: sata@bffd1800 {
200 compatible = "amcc,sata-460ex";
201 reg = <4 0xbffd1800 0x800>;
202 interrupt-parent = <&UIC0>;
203 interrupts = <27 4>;
204 dmas = <&AHBDMA 1 0 2>;
205 dma-names = "sata-dma";
206 };
207
208
209 USBOTG0: usbotg@bff80000 {
210 compatible = "snps,dwc2";
211 reg = <4 0xbff80000 0x10000>;
212 interrupt-parent = <&USBOTG0>;
213 interrupts = <0 1 2>;
214 #interrupt-cells = <1>;
215 #address-cells = <0>;
216 #size-cells = <0>;
217 interrupt-map = </* USB-OTG */ 0 &UIC2 0x1c 4
218 /* HIGH-POWER */ 1 &UIC1 0x1a 8
219 /* DMA */ 2 &UIC0 0xc 4>;
220 dr_mode = "host";
221 };
222
223 POB0: opb {
224 compatible = "ibm,opb-460ex", "ibm,opb";
225 #address-cells = <1>;
226 #size-cells = <1>;
227 ranges = <0xb0000000 0x4 0xb0000000 0x50000000>;
228 clock-frequency = <0>; /* Filled in by U-Boot */
229
230 EBC0: ebc {
231 compatible = "ibm,ebc-460ex", "ibm,ebc";
232 dcr-reg = <0x012 0x002>;
233 #address-cells = <2>;
234 #size-cells = <1>;
235 clock-frequency = <0>; /* Filled in by U-Boot */
236 interrupts = <0x6 0x4>;
237 interrupt-parent = <&UIC1>;
238 /* ranges property are supplied by U-Boot */
239 ranges = <0x0 0x0 0xfff80000 0x00080000
240 0x1 0x0 0x00000000 0x00000000
241 0x2 0x0 0x00000000 0x00000000>;
242
243 /* Define device tree for Apollo3g NAS NOR flash
244 * The NOR doesn't work when "enable-button" GPIO
245 * is asserted.
246 */
247 nor_flash@0,0 {
248 compatible = "amd,s29gl512n", "jedec-probe", "cfi-flash", "mtd-rom";
249 bank-width = <1>;
250 reg = <0x00000000 0x00000000 0x00080000>;
251 #address-cells = <1>;
252 #size-cells = <1>;
253
254 partition@0 {
255 /* Part of bootrom - Don't use it without a jump */
256 label = "free";
257 reg = <0x00000000 0x0001e000>;
258 };
259 partition@1 {
260 label = "env";
261 reg = <0x0001e000 0x00002000>;
262 };
263 partition@2 {
264 label = "uboot";
265 reg = <0x00020000 0x00050000>;
266 };
267
268 };
269
270 ndfc@1,0 {
271 compatible = "ibm,ndfc";
272 reg = <0x00000001 0x00000000 0x00002000>;
273 ccr = <0x00001000>;
274 bank-settings = <0x80002222>;
275 #address-cells = <1>;
276 #size-cells = <1>;
277 status = "disabled";
278
279 nand {
280 #address-cells = <1>;
281 #size-cells = <1>;
282 };
283 };
284 };
285
286 gpio0: gpio0@e0000000 {
287 compatible = "wd,mbl-gpio", "ti,74273";
288 reg-names = "dat";
289 reg = <0xe0000000 0x1>;
290 #gpio-cells = <2>;
291 gpio-controller;
292
293 enable-phy {
294 /* toggle to reset EMAC PHY */
295 gpio-hog;
296 line-name = "enable EMAC PHY";
297 gpios = <0 1>;
298 output-low;
299 };
300
301 enable-button {
302 /* Defined in u-boot as: NOT_NOR
303 * "enables features other than NOR
304 * specifically, the buffer at CS2"
305 * (button).
306 *
307 * Note: This option is disabled as
308 * it prevents the system from being
309 * rebooted successfully.
310 */
311
312 gpio-hog;
313 line-name = "Enable Reset Button, disable NOR";
314 gpios = <1 0>;
315 output-low;
316 };
317
318 enable-usb {
319 gpio-hog;
320 line-name = "Power USB Core";
321 gpios = <2 1>;
322 output-low;
323 };
324
325 enable-port1 {
326 gpio-hog;
327 line-name = "Power Drive Port 1";
328 gpios = <3 1>;
329 output-low;
330 };
331
332 enable-port0 {
333 gpio-hog;
334 line-name = "Power Drive Port 0";
335 gpios = <7 1>;
336 output-low;
337 };
338 };
339
340 gpio1: gpio1@e0100000 {
341 compatible = "wd,mbl-gpio", "ti,74244";
342 reg-names = "dat";
343 reg = <0xe0100000 0x1>;
344 #gpio-cells = <2>;
345 gpio-controller;
346 no-output;
347 };
348
349 UART0: serial@ef600300 {
350 device_type = "serial";
351 compatible = "ns16550";
352 reg = <0xef600300 0x00000008>;
353 virtual-reg = <0xef600300>;
354 clock-frequency = <0>; /* Filled in by U-Boot */
355 current-speed = <0>; /* Filled in by U-Boot */
356 interrupt-parent = <&UIC1>;
357 interrupts = <0x1 0x4>;
358 };
359
360 gpio-leds {
361 compatible = "gpio-leds";
362 power-red {
363 label = "mbl:red:power";
364 gpios = <&gpio0 4 0>;
365 linux,default-trigger = "panic";
366 };
367 power-green {
368 label = "mbl:green:power";
369 gpios = <&gpio0 5 0>;
370 linux,default-trigger = "default-on";
371 };
372 power-blue {
373 label = "mbl:blue:power";
374 gpios = <&gpio0 6 0>;
375 linux,default-trigger = "cpu0";
376 };
377 };
378
379 gpio_keys_polled {
380 compatible = "gpio-keys-polled";
381 #address-cells = <1>;
382 #size-cells = <0>;
383 poll-interval = <60>; /* 3 * 20 = 60ms */
384 autorepeat;
385 button@1 {
386 label = "Reset button";
387 linux,code = <0x198>; /* KEY_RESTART */
388 gpios = <&gpio1 2 1>;
389 };
390 };
391
392 RGMII0: emac-rgmii@ef601500 {
393 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
394 reg = <0xef601500 0x00000008>;
395 has-mdio;
396 };
397
398 TAH0: emac-tah@ef601350 {
399 compatible = "ibm,tah-460ex", "ibm,tah";
400 reg = <0xef601350 0x00000030>;
401 };
402
403 EMAC0: ethernet@ef600c00 {
404 device_type = "network";
405 compatible = "ibm,emac-405ex", "ibm,emac4sync";
406 interrupt-parent = <&EMAC0>;
407 interrupts = <0x0 0x1>;
408 #interrupt-cells = <1>;
409 #address-cells = <0>;
410 #size-cells = <0>;
411 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
412 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
413 reg = <0xef600c00 0x000000c4>;
414 local-mac-address = [000000000000]; /* Filled in by U-Boot */
415 mal-device = <&MAL0>;
416 mal-tx-channel = <0>;
417 mal-rx-channel = <0>;
418 cell-index = <0>;
419 max-frame-size = <9000>;
420 rx-fifo-size = <16384>;
421 tx-fifo-size = <2048>;
422 phy-mode = "rgmii";
423 phy-map = <0x00000000>;
424 rgmii-device = <&RGMII0>;
425 rgmii-channel = <0>;
426 tah-device = <&TAH0>;
427 tah-channel = <0>;
428 has-inverted-stacr-oc;
429 has-new-stacr-staopc;
430 };
431 };
432
433 ADMA: adma {
434 compatible = "amcc,apm82181-adma";
435 device_type = "dma";
436 #address-cells = <2>;
437 #size-cells = <1>;
438
439 dma-4channel@1 {
440 compatible = "amcc,apm82181-dma-4channel";
441 cell-index = <1>;
442 label = "plb_dma1";
443 interrupt-parent = <&UIC0>;
444 interrupts = <0xd 0x4>;
445 pool_size = <0x4000>;
446 dcr-reg = <0x208 0x20f>;
447 };
448
449 dma-4channel@2 {
450 compatible = "amcc,apm82181-dma-4channel";
451 cell-index = <2>;
452 label = "plb_dma2";
453 interrupt-parent = <&UIC0>;
454 interrupts = <0xe 0x4>;
455 pool_size = <0x4000>;
456 dcr-reg = <0x210 0x217>;
457 };
458
459 dma-4channel@3 {
460 compatible = "amcc,apm82181-dma-4channel";
461 cell-index = <3>;
462 label = "plb_dma3";
463 interrupt-parent = <&UIC0>;
464 interrupts = <0xf 0x4>;
465 pool_size = <0x4000>;
466 dcr-reg = <0x218 0x21f>;
467 };
468 };
469
470 DMA: plb_dma@400300200 {
471 #address-cells = <1>;
472 #size-cells = <1>;
473 compatible = "amcc,dma";
474 cell-index = <0>;
475 reg = <4 00300200 200>;
476 dcr-reg = <0x100 0x13f>;
477 interrupt-parent = <&UIC0>;
478 interrupts = <0>;
479 interrupt-map = < /* chan0 */ 0 &UIC0 12 4>;
480
481 dma-4channel@0{
482 compatible = "amcc,dma-4channel";
483 cell-index = <0>;
484 label = "channel0";
485 reg = <0x100 0x107>;
486 };
487 };
488 };
489 };
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