package/boot/uboot-mediatek/patches/001-mtk-0004-mips-add-support-for-noncached_alloc.patch

   1 From d7cfa1cb5602a1d936df36ee70869753835de28e Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 20 May 2022 11:21:51 +0800
   4 Subject: [PATCH 04/25] mips: add support for noncached_alloc()
   5
   6 This patch adds support for noncached_alloc() which was only supported by
   7 ARM platform.
   8
   9 Unlike the ARM platform, MMU is not used in u-boot for MIPS. Instead, KSEG
  10 is provided to access uncached memory. So most code of this patch is copied
  11 from cache.c of ARM platform, with only two differences:
  12 1. MMU is untouched in noncached_set_region()
  13 2. Address returned by noncached_alloc() is converted using KSEG1ADDR()
  14
  15 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  16 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  17 ---
  18  arch/mips/include/asm/system.h | 20 ++++++++++++++++
  19  arch/mips/lib/cache.c          | 43 ++++++++++++++++++++++++++++++++++
  20  2 files changed, 63 insertions(+)
  21
  22 diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
  23 index 79e638844b..89a2ac209f 100644
  24 --- a/arch/mips/include/asm/system.h
  25 +++ b/arch/mips/include/asm/system.h
  26 @@ -282,4 +282,24 @@ static inline void instruction_hazard_barrier(void)
  27         : "=&r"(tmp));
  28  }
  29
  30 +#ifdef CONFIG_SYS_NONCACHED_MEMORY
  31 +/* 1MB granularity */
  32 +#define MMU_SECTION_SHIFT      20
  33 +#define MMU_SECTION_SIZE       (1 << MMU_SECTION_SHIFT)
  34 +
  35 +/**
  36 + * noncached_init() - Initialize non-cached memory region
  37 + *
  38 + * Initialize non-cached memory area. This memory region will be typically
  39 + * located right below the malloc() area and be accessed from KSEG1.
  40 + *
  41 + * It is called during the generic post-relocation init sequence.
  42 + *
  43 + * Return: 0 if OK
  44 + */
  45 +int noncached_init(void);
  46 +
  47 +phys_addr_t noncached_alloc(size_t size, size_t align);
  48 +#endif /* CONFIG_SYS_NONCACHED_MEMORY */
  49 +
  50  #endif /* _ASM_SYSTEM_H */
  51 diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
  52 index ec652f0fba..d23b38d6b9 100644
  53 --- a/arch/mips/lib/cache.c
  54 +++ b/arch/mips/lib/cache.c
  55 @@ -6,6 +6,7 @@
  56
  57  #include <common.h>
  58  #include <cpu_func.h>
  59 +#include <malloc.h>
  60  #include <asm/cache.h>
  61  #include <asm/cacheops.h>
  62  #include <asm/cm.h>
  63 @@ -197,3 +198,45 @@ void dcache_disable(void)
  64         /* ensure the pipeline doesn't contain now-invalid instructions */
  65         instruction_hazard_barrier();
  66  }
  67 +
  68 +#ifdef CONFIG_SYS_NONCACHED_MEMORY
  69 +static unsigned long noncached_start;
  70 +static unsigned long noncached_end;
  71 +static unsigned long noncached_next;
  72 +
  73 +void noncached_set_region(void)
  74 +{
  75 +}
  76 +
  77 +int noncached_init(void)
  78 +{
  79 +       phys_addr_t start, end;
  80 +       size_t size;
  81 +
  82 +       /* If this calculation changes, update board_f.c:reserve_noncached() */
  83 +       end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
  84 +       size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
  85 +       start = end - size;
  86 +
  87 +       debug("mapping memory %pa-%pa non-cached\n", &start, &end);
  88 +
  89 +       noncached_start = start;
  90 +       noncached_end = end;
  91 +       noncached_next = start;
  92 +
  93 +       return 0;
  94 +}
  95 +
  96 +phys_addr_t noncached_alloc(size_t size, size_t align)
  97 +{
  98 +       phys_addr_t next = ALIGN(noncached_next, align);
  99 +
 100 +       if (next >= noncached_end || (noncached_end - next) < size)
 101 +               return 0;
 102 +
 103 +       debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
 104 +       noncached_next = next + size;
 105 +
 106 +       return CKSEG1ADDR(next);
 107 +}
 108 +#endif /* CONFIG_SYS_NONCACHED_MEMORY */
 109 --
 110 2.36.1
 111