layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / package / boot / uboot-layerscape / patches / 0082-armv8-ls1012a-Update-DDR-timing.patch
1 From 9e157635c191762624c066d14e360e972aa1ad0f Mon Sep 17 00:00:00 2001
2 From: Shengzhou Liu <Shengzhou.Liu@nxp.com>
3 Date: Wed, 20 Jul 2016 15:44:58 +0800
4 Subject: [PATCH 82/93] armv8: ls1012a: Update DDR timing
5
6 Update MMDC timing CL-tRCD-tRP to 7-7-7.
7
8 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
9 ---
10 board/freescale/ls1012afrdm/ls1012afrdm.c | 2 +-
11 board/freescale/ls1012aqds/ls1012aqds.c | 2 +-
12 board/freescale/ls1012ardb/ls1012ardb.c | 2 +-
13 3 files changed, 3 insertions(+), 3 deletions(-)
14
15 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
16 index 04f8f9a..a152a18 100644
17 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c
18 +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
19 @@ -55,7 +55,7 @@ void mmdc_init(void)
20 /* configure timing parms */
21 out_be32(&mmdc->mdotc, 0x12554000);
22 out_be32(&mmdc->mdcfg0, 0xbabf7954);
23 - out_be32(&mmdc->mdcfg1, 0xff328f64);
24 + out_be32(&mmdc->mdcfg1, 0xdb328f64);
25 out_be32(&mmdc->mdcfg2, 0x01ff00db);
26
27 /* other parms */
28 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
29 index 4ae8def..7bdb591 100644
30 --- a/board/freescale/ls1012aqds/ls1012aqds.c
31 +++ b/board/freescale/ls1012aqds/ls1012aqds.c
32 @@ -78,7 +78,7 @@ void mmdc_init(void)
33 /* configure timing parms */
34 out_be32(&mmdc->mdotc, 0x12554000);
35 out_be32(&mmdc->mdcfg0, 0xbabf7954);
36 - out_be32(&mmdc->mdcfg1, 0xff328f64);
37 + out_be32(&mmdc->mdcfg1, 0xdb328f64);
38 out_be32(&mmdc->mdcfg2, 0x01ff00db);
39
40 /* other parms */
41 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
42 index 06e1f6b..ac51d56 100644
43 --- a/board/freescale/ls1012ardb/ls1012ardb.c
44 +++ b/board/freescale/ls1012ardb/ls1012ardb.c
45 @@ -84,7 +84,7 @@ void mmdc_init(void)
46 /* configure timing parms */
47 out_be32(&mmdc->mdotc, 0x12554000);
48 out_be32(&mmdc->mdcfg0, 0xbabf7954);
49 - out_be32(&mmdc->mdcfg1, 0xff328f64);
50 + out_be32(&mmdc->mdcfg1, 0xdb328f64);
51 out_be32(&mmdc->mdcfg2, 0x01ff00db);
52
53 /* other parms */
54 --
55 1.7.9.5
56