layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / package / boot / uboot-layerscape / patches / 0074-board-freescale-ls1012a-Intergrate-and-enable-PPA-on.patch
1 From f95f8ebd8d55ccc27e1615b251450915a1c14315 Mon Sep 17 00:00:00 2001
2 From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
3 Date: Tue, 12 Jul 2016 14:17:17 +0530
4 Subject: [PATCH 74/93] board: freescale: ls1012a: Intergrate and enable PPA
5 on LS1012AFRDM
6
7 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
8 ---
9 board/freescale/ls1012afrdm/ls1012afrdm.c | 9 +++++++++
10 include/configs/ls1012afrdm.h | 12 ++++++++++++
11 2 files changed, 21 insertions(+)
12
13 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
14 index 4b7902a..04f8f9a 100644
15 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c
16 +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
17 @@ -143,6 +143,9 @@ int board_early_init_f(void)
18 int board_init(void)
19 {
20 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
21 +#ifdef CONFIG_FSL_LS_PPA
22 + u64 ppa_entry;
23 +#endif
24 /*
25 * Set CCI-400 control override register to enable barrier
26 * transaction
27 @@ -157,6 +160,12 @@ int board_init(void)
28 enable_layerscape_ns_access();
29 #endif
30
31 +#ifdef CONFIG_FSL_LS_PPA
32 + ppa_init_pre(&ppa_entry);
33 +
34 + if (ppa_entry)
35 + ppa_init_entry((void *)ppa_entry);
36 +#endif
37 return 0;
38 }
39
40 diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
41 index 622c774..26e3640 100644
42 --- a/include/configs/ls1012afrdm.h
43 +++ b/include/configs/ls1012afrdm.h
44 @@ -9,6 +9,18 @@
45
46 #include "ls1012a_common.h"
47
48 +#ifndef CONFIG_SECURE_BOOT
49 +#define CONFIG_FSL_LS_PPA
50 +#if defined(CONFIG_FSL_LS_PPA)
51 +#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024)
52 +
53 +#define CONFIG_SYS_LS_PPA_FW_IN_XIP
54 +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
55 +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000
56 +#endif
57 +#endif
58 +#endif
59 +
60 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
61 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
62 #define CONFIG_NR_DRAM_BANKS 2
63 --
64 1.7.9.5
65