package/boot/uboot-layerscape/patches/0054-armv8-fsl-layerscape-Update-DDR-timings.patch

   1 From 0ecab71ba6f860a831288337d96b0f4b0fbf12c6 Mon Sep 17 00:00:00 2001
   2 From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
   3 Date: Mon, 13 Jun 2016 17:29:59 +0530
   4 Subject: [PATCH 54/93] armv8: fsl-layerscape: Update DDR timings
   5
   6 DDR timigs displayed for LS1012A were half of true value.
   7 Updated DDR value to 1000 MT/s.
   8
   9 Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
  10 ---
  11  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |    5 +++--
  12  1 file changed, 3 insertions(+), 2 deletions(-)
  13
  14 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
  15 index 63e5bed..a4dde5b 100644
  16 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
  17 +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
  18 @@ -92,9 +92,10 @@ void get_sys_info(struct sys_info *sys_info)
  19                         freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  20         }
  21
  22 -       if (ver == SVR_LS1012)
  23 +       if (ver == SVR_LS1012){
  24                 sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
  25 -
  26 +               sys_info->freq_ddrbus *=2;
  27 +       }
  28  #define HWA_CGA_M1_CLK_SEL     0xe0000000
  29  #define HWA_CGA_M1_CLK_SHIFT   29
  30  #ifdef CONFIG_SYS_DPAA_FMAN
  31 --
  32 1.7.9.5
  33