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layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / package / boot / uboot-layerscape / patches / 0049-DNCPE-296-PFE-reset-woraround-fix.patch
1 From 1b9cf577511123dd05e1d3b1fe7fd5db43b6097f Mon Sep 17 00:00:00 2001
2 From: Anji J <anji.jagarlmudi@freescale.com>
3 Date: Wed, 25 May 2016 13:40:13 +0530
4 Subject: [PATCH 49/93] DNCPE-296 PFE reset woraround fix
5
6 - Linux driver depends on U-boot TMU initialization,
7 but U-boot tmu initialization is not as expected by Linux driver.
8 - Align U-boot TMU initialization with Linux driver
9 - LLM base address in DDR changed to match with Linux driver expectation.
10 - Remove unwanted pfe_mod.h
11 - Start PFE/network at bootup time.
12 ---
13 common/cmd_pfe_commands.c | 9 +-
14 drivers/net/pfe_eth/pfe.c | 16 ++--
15 drivers/net/pfe_eth/pfe/cbus/tmu_csr.h | 7 ++
16 drivers/net/pfe_eth/pfe_eth.h | 9 +-
17 drivers/net/pfe_eth/pfe_mod.h | 140 --------------------------------
18 include/configs/ls1012a_common.h | 1 -
19 6 files changed, 24 insertions(+), 158 deletions(-)
20 delete mode 100644 drivers/net/pfe_eth/pfe_mod.h
21
22 diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
23 index 0e22097..ca479d7 100644
24 --- a/common/cmd_pfe_commands.c
25 +++ b/common/cmd_pfe_commands.c
26 @@ -932,7 +932,7 @@ static void send_dummy_pkt_to_hif(void)
27 /*Allocate BMU2 buffer */
28 buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
29
30 - printf("Sending a dummy pkt to HIF %x\n", buf);
31 + debug("Sending a dummy pkt to HIF %x\n", buf);
32 buf += 0x80;
33 memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
34 /*Write length and pkt to TMU*/
35 @@ -945,14 +945,13 @@ static void pfe_command_stop(int argc, char * const argv[])
36 {
37 int id;
38 u32 rx_status;
39 - printf("Stopping PFE \n");
40 + printf("Stopping PFE... \n");
41
42 /*Mark all descriptors as LAST_BD */
43 hif_rx_desc_disable();
44
45 /*If HIF Rx BDP is busy send a dummy packet */
46 rx_status = readl(HIF_RX_STATUS);
47 - printf("rx_status %x %x\n",rx_status, BDP_CSR_RX_DMA_ACTV);
48 if(rx_status & BDP_CSR_RX_DMA_ACTV)
49 send_dummy_pkt_to_hif();
50 udelay(10);
51 @@ -964,12 +963,10 @@ static void pfe_command_stop(int argc, char * const argv[])
52
53 for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
54 {
55 - printf("Stop %d\n", id);
56 /*Inform PE to stop */
57 pe_dmem_write(id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
58 udelay(10);
59
60 - printf("Reading %d\n", id);
61 /*Read status */
62 if(!pe_dmem_read(id, PEMBOX_ADDR_CLASS+4, 4))
63 printf("Failed to stop PE%d\n", id);
64 @@ -979,12 +976,10 @@ static void pfe_command_stop(int argc, char * const argv[])
65 {
66 if(id == TMU2_ID) continue;
67
68 - printf("Stop %d\n", id);
69 /*Inform PE to stop */
70 pe_dmem_write(id, 1, PEMBOX_ADDR_TMU, 4);
71 udelay(10);
72
73 - printf("Reading %d\n", id);
74 /*Read status */
75 if(!pe_dmem_read(id, PEMBOX_ADDR_TMU+4, 4))
76 printf("Failed to stop PE%d\n", id);
77 diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
78 index 3b5570a..2c31cad 100644
79 --- a/drivers/net/pfe_eth/pfe.c
80 +++ b/drivers/net/pfe_eth/pfe.c
81 @@ -1489,17 +1489,16 @@ void tmu_init(TMU_CFG *cfg)
82 writel(0x3FF, TMU_TDQ2_SCH_CTRL);
83 #endif
84 writel(0x3FF, TMU_TDQ3_SCH_CTRL);
85 -
86 -
87 +
88 if (PLL_CLK_EN == 0)
89 writel(0x0, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:1 the value is 0
90 else
91 writel(0x1, TMU_PE_SYS_CLK_RATIO); // Clock ratio: for 1:2 the value is 1
92
93 - //printf("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
94 + debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
95 writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR); // Extra packet pointers will be stored from this address onwards
96 -
97 - //printf("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
98 +
99 + debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
100 writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
101 writel(5, TMU_TDQ_IIFG_CFG);
102 writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
103 @@ -1531,7 +1530,12 @@ void tmu_init(TMU_CFG *cfg)
104 u32 qmax;
105 writel((phyno << 8) | q, TMU_TEQ_CTRL);
106 writel(1 << 22, TMU_TEQ_QCFG);
107 - qmax = ((phyno == 3) || (q < 8)) ? 255 : 127;
108 +
109 + if (phyno == 3)
110 + qmax = DEFAULT_TMU3_QDEPTH;
111 + else
112 + qmax = (q == 0) ? DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
113 +
114 writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
115 writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
116 }
117 diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
118 index cbcbb1f..64fad04 100644
119 --- a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
120 +++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
121 @@ -93,10 +93,17 @@
122 #define MEM_INIT_DONE (1 << 7)
123 #define LLM_INIT (1 << 8)
124 #define LLM_INIT_DONE (1 << 9)
125 +#define ECC_MEM_INIT_DONE (1<<10)
126
127 typedef struct {
128 u32 llm_base_addr;
129 u32 llm_queue_len;
130 } TMU_CFG;
131
132 +/* Not HW related for pfe_ctrl / pfe common defines */
133 +#define DEFAULT_MAX_QDEPTH 80
134 +#define DEFAULT_Q0_QDEPTH 511 //We keep one large queue for host tx qos
135 +#define DEFAULT_TMU3_QDEPTH 127
136 +
137 +
138 #endif /* _TMU_CSR_H_ */
139 diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
140 index dfcc00e..c16b8c0 100644
141 --- a/drivers/net/pfe_eth/pfe_eth.h
142 +++ b/drivers/net/pfe_eth/pfe_eth.h
143 @@ -39,11 +39,8 @@
144 #define BMU2_BUF_COUNT (3 * SZ_1K)
145 #define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
146
147 -#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
148 -#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
149 -#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
150
151 -#define HIF_RX_PKT_DDR_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
152 +#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
153 #define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
154 #define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
155 #define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
156 @@ -72,6 +69,10 @@
157 #define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
158 #define TMU_DDR_DATA_SIZE (32 * SZ_1K)
159
160 +#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
161 +#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
162 +#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
163 +
164 //#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
165 #define ROUTE_TABLE_BASEADDR 0x800000
166 #define ROUTE_TABLE_HASH_BITS_MAX 15 /**< 32K entries */
167 diff --git a/drivers/net/pfe_eth/pfe_mod.h b/drivers/net/pfe_eth/pfe_mod.h
168 deleted file mode 100644
169 index 9436b72..0000000
170 --- a/drivers/net/pfe_eth/pfe_mod.h
171 +++ /dev/null
172 @@ -1,140 +0,0 @@
173 -/*
174 - * (C) Copyright 2011
175 - * Author : Mindspeed Technologes
176 - *
177 - * See file CREDITS for list of people who contributed to this
178 - * project.
179 - *
180 - * This program is free software; you can redistribute it and/or
181 - * modify it under the terms of the GNU General Public License as
182 - * published by the Free Software Foundation; either version 2 of
183 - * the License, or (at your option) any later version.
184 - *
185 - * This program is distributed in the hope that it will be useful,
186 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
187 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
188 - * GNU General Public License for more details.
189 - *
190 - * You should have received a copy of the GNU General Public License
191 - * along with this program; if not, write to the Free Software
192 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
193 - * MA 02111-1307 USA
194 - * */
195 -
196 -
197 -#ifndef _PFE_MOD_H_
198 -#define _PFE_MOD_H_
199 -
200 -#include <linux/device.h>
201 -
202 -#include "pfe/pfe.h"
203 -#include "pfe/cbus.h"
204 -#include "pfe/cbus/bmu.h"
205 -
206 -#include "pfe_driver.h"
207 -
208 -struct pfe;
209 -
210 -
211 -struct pfe {
212 - unsigned long ddr_phys_baseaddr;
213 - void *ddr_baseaddr;
214 - void *cbus_baseaddr;
215 - void *apb_baseaddr;
216 - void *iram_baseaddr;
217 - int hif_irq;
218 - struct device *dev;
219 - struct pci_dev *pdev;
220 -
221 -#if 0
222 - struct pfe_ctrl ctrl;
223 - struct pfe_hif hif;
224 - struct pfe_eth eth;
225 -#endif
226 -};
227 -
228 -extern struct pfe *pfe;
229 -
230 -int pfe_probe(struct pfe *pfe);
231 -int pfe_remove(struct pfe *pfe);
232 -
233 -#ifndef SZ_1K
234 -#define SZ_1K 1024
235 -#endif
236 -
237 -#ifndef SZ_1M
238 -#define SZ_1M (1024 * 1024)
239 -#endif
240 -
241 -/* DDR Mapping */
242 -#if !defined(CONFIG_PLATFORM_PCI)
243 -#define UTIL_CODE_BASEADDR 0
244 -#define UTIL_CODE_SIZE (128 * SZ_1K)
245 -#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
246 -#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
247 -#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
248 -#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
249 -#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
250 -#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
251 -#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
252 -#define ROUTE_TABLE_HASH_BITS 15 /**< 32K entries */
253 -#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
254 -#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
255 -#define BMU2_BUF_COUNT (4096 - 256) /**< This is to get a total DDR size of 12MiB */
256 -#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
257 -#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
258 -#define TMU_LLM_QUEUE_LEN (16 * 256) /**< Must be power of two and at least 16 * 8 = 128 bytes */
259 -#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
260 -
261 -#if (TMU_LLM_BASEADDR + TMU_LLM_SIZE) > 0xC00000
262 -#error DDR mapping above 12MiB
263 -#endif
264 -
265 -#else
266 -
267 -#define UTIL_CODE_BASEADDR 0
268 -#if defined(CONFIG_UTIL_PE_DISABLED)
269 -#define UTIL_CODE_SIZE (0 * SZ_1K)
270 -#else
271 -#define UTIL_CODE_SIZE (8 * SZ_1K)
272 -#endif
273 -#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
274 -#define UTIL_DDR_DATA_SIZE (0 * SZ_1K)
275 -#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
276 -#define CLASS_DDR_DATA_SIZE (0 * SZ_1K)
277 -#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
278 -#define TMU_DDR_DATA_SIZE (0 * SZ_1K)
279 -#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
280 -#define ROUTE_TABLE_HASH_BITS 5 /**< 32 entries */
281 -#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
282 -#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
283 -#define BMU2_BUF_COUNT 8
284 -#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
285 -#define TMU_LLM_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
286 -#define TMU_LLM_QUEUE_LEN (16 * 8) /**< Must be power of two and at least 16 * 8 = 128 bytes */
287 -#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) /**< (4 TMU's x 16 queues x queue_len) */
288 -#define HIF_DESC_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
289 -#define HIF_RX_DESC_SIZE (16*HIF_RX_DESC_NT)
290 -#define HIF_TX_DESC_SIZE (16*HIF_TX_DESC_NT)
291 -#define HIF_DESC_SIZE (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
292 -#define HIF_RX_PKT_DDR_BASEADDR (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
293 -#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
294 -#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
295 -#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
296 -#define ROUTE_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
297 -#define ROUTE_SIZE (2 * CLASS_ROUTE_SIZE)
298 -
299 -#if (ROUTE_BASEADDR + ROUTE_SIZE) > 0x10000
300 -#error DDR mapping above 64KiB
301 -#endif
302 -
303 -#define PFE_HOST_TO_PCI(addr) (((u32)addr)- ((u32)DDR_BASE_ADDR))
304 -#define PFE_PCI_TO_HOST(addr) (((u32)addr)+ ((u32)DDR_BASE_ADDR))
305 -#endif
306 -
307 -/* LMEM Mapping */
308 -#define BMU1_LMEM_BASEADDR 0
309 -#define BMU1_BUF_COUNT 256
310 -#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
311 -
312 -#endif /* _PFE_MOD_H */
313 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
314 index 3c4ab6c..57fc057 100644
315 --- a/include/configs/ls1012a_common.h
316 +++ b/include/configs/ls1012a_common.h
317 @@ -113,7 +113,6 @@
318 #define CONFIG_FSL_PPFE
319
320 #ifdef CONFIG_FSL_PPFE
321 -#define CONFIG_CMD_PFE_START
322 #define CONFIG_CMD_PFE_COMMANDS
323 #define CONFIG_UTIL_PE_DISABLED
324
325 --
326 1.7.9.5
327
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