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layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / package / boot / uboot-layerscape / patches / 0039-armv8-ls1012a-Add-support-of-ls1012afrdm-board.patch
1 From 6aaa5973b9ae8452a546e0666b2389bb163fb949 Mon Sep 17 00:00:00 2001
2 From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
3 Date: Thu, 19 May 2016 16:45:27 +0530
4 Subject: [PATCH 39/93] armv8: ls1012a: Add support of ls1012afrdm board
5
6 QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
7 development platform, with a complete debugging environment.
8 The LS1012AFRDM board supports the QorIQ LS1012A processor and is
9 optimized to support the high-bandwidth DDR3L memory and
10 a full complement of high-speed SerDes ports.
11
12 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
13 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
14 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
15 Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
16 ---
17 arch/arm/Kconfig | 10 ++
18 arch/arm/dts/Makefile | 3 +-
19 arch/arm/dts/fsl-ls1012a-frdm.dts | 16 +++
20 arch/arm/dts/fsl-ls1012a-frdm.dtsi | 39 ++++++
21 board/freescale/ls1012afrdm/Kconfig | 15 +++
22 board/freescale/ls1012afrdm/MAINTAINERS | 6 +
23 board/freescale/ls1012afrdm/Makefile | 7 ++
24 board/freescale/ls1012afrdm/README | 94 +++++++++++++++
25 board/freescale/ls1012afrdm/ls1012afrdm.c | 183 +++++++++++++++++++++++++++++
26 configs/ls1012afrdm_qspi_defconfig | 10 ++
27 include/configs/ls1012afrdm.h | 59 ++++++++++
28 11 files changed, 441 insertions(+), 1 deletion(-)
29 create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
30 create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
31 create mode 100644 board/freescale/ls1012afrdm/Kconfig
32 create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
33 create mode 100644 board/freescale/ls1012afrdm/Makefile
34 create mode 100644 board/freescale/ls1012afrdm/README
35 create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
36 create mode 100644 configs/ls1012afrdm_qspi_defconfig
37 create mode 100644 include/configs/ls1012afrdm.h
38
39 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
40 index b536684..23fce38 100644
41 --- a/arch/arm/Kconfig
42 +++ b/arch/arm/Kconfig
43 @@ -669,6 +669,15 @@ config TARGET_LS1012ARDB
44 development platform that supports the QorIQ LS1012A
45 Layerscape Architecture processor.
46
47 +config TARGET_LS1012AFRDM
48 + bool "Support ls1012afrdm"
49 + select ARM64
50 + help
51 + Support for Freescale LS1012AFRDM platform.
52 + The LS1012A Freedom board (FRDM) is a high-performance
53 + development platform that supports the QorIQ LS1012A
54 + Layerscape Architecture processor.
55 +
56 config TARGET_LS1021AQDS
57 bool "Support ls1021aqds"
58 select CPU_V7
59 @@ -816,6 +825,7 @@ source "board/freescale/ls1021atwr/Kconfig"
60 source "board/freescale/ls1043ardb/Kconfig"
61 source "board/freescale/ls1012aqds/Kconfig"
62 source "board/freescale/ls1012ardb/Kconfig"
63 +source "board/freescale/ls1012afrdm/Kconfig"
64 source "board/freescale/mx23evk/Kconfig"
65 source "board/freescale/mx25pdk/Kconfig"
66 source "board/freescale/mx28evk/Kconfig"
67 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
68 index 9e8137b..de023b4 100644
69 --- a/arch/arm/dts/Makefile
70 +++ b/arch/arm/dts/Makefile
71 @@ -96,7 +96,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
72 fsl-ls1043a-qds-lpuart.dtb \
73 fsl-ls1043a-rdb.dtb \
74 fsl-ls1012a-qds.dtb \
75 - fsl-ls1012a-rdb.dtb
76 + fsl-ls1012a-rdb.dtb \
77 + fsl-ls1012a-frdm.dtb
78
79 dtb-$(CONFIG_MACH_SUN4I) += \
80 sun4i-a10-a1000.dtb \
81 diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
82 new file mode 100644
83 index 0000000..3a06c0a
84 --- /dev/null
85 +++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
86 @@ -0,0 +1,16 @@
87 +/*
88 + * Device Tree file for Freescale Layerscape-1012A family SoC.
89 + *
90 + * Copyright (C) 2016, Freescale Semiconductor
91 + *
92 + * SPDX-License-Identifier: GPL-2.0+
93 + */
94 +
95 +/dts-v1/;
96 +#include "fsl-ls1012a-frdm.dtsi"
97 +
98 +/ {
99 + chosen {
100 + stdout-path = &duart0;
101 + };
102 +};
103 diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
104 new file mode 100644
105 index 0000000..9f0db91
106 --- /dev/null
107 +++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
108 @@ -0,0 +1,39 @@
109 +/*
110 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
111 + *
112 + * Copyright (C) 2016, Freescale Semiconductor
113 + *
114 + * This file is licensed under the terms of the GNU General Public
115 + * License version 2. This program is licensed "as is" without any
116 + * warranty of any kind, whether express or implied.
117 + */
118 +
119 +/include/ "fsl-ls1012a.dtsi"
120 +
121 +/ {
122 + model = "LS1012A FREEDOM Board";
123 + aliases {
124 + spi0 = &qspi;
125 + };
126 +};
127 +
128 +&qspi {
129 + bus-num = <0>;
130 + status = "okay";
131 +
132 + qflash0: s25fl128s@0 {
133 + #address-cells = <1>;
134 + #size-cells = <1>;
135 + compatible = "spi-flash";
136 + spi-max-frequency = <20000000>;
137 + reg = <0>;
138 + };
139 +};
140 +
141 +&i2c0 {
142 + status = "okay";
143 +};
144 +
145 +&duart0 {
146 + status = "okay";
147 +};
148 diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
149 new file mode 100644
150 index 0000000..a34521c
151 --- /dev/null
152 +++ b/board/freescale/ls1012afrdm/Kconfig
153 @@ -0,0 +1,15 @@
154 +if TARGET_LS1012AFRDM
155 +
156 +config SYS_BOARD
157 + default "ls1012afrdm"
158 +
159 +config SYS_VENDOR
160 + default "freescale"
161 +
162 +config SYS_SOC
163 + default "fsl-layerscape"
164 +
165 +config SYS_CONFIG_NAME
166 + default "ls1012afrdm"
167 +
168 +endif
169 diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
170 new file mode 100644
171 index 0000000..2f31d0f
172 --- /dev/null
173 +++ b/board/freescale/ls1012afrdm/MAINTAINERS
174 @@ -0,0 +1,6 @@
175 +LS1012AFRDM BOARD
176 +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
177 +S: Maintained
178 +F: board/freescale/ls1012afrdm/
179 +F: include/configs/ls1012afrdm.h
180 +F: configs/ls1012afrdm_defconfig
181 diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
182 new file mode 100644
183 index 0000000..dbfa2ce
184 --- /dev/null
185 +++ b/board/freescale/ls1012afrdm/Makefile
186 @@ -0,0 +1,7 @@
187 +#
188 +# Copyright 2016 Freescale Semiconductor, Inc.
189 +#
190 +# SPDX-License-Identifier: GPL-2.0+
191 +#
192 +
193 +obj-y += ls1012afrdm.o
194 diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
195 new file mode 100644
196 index 0000000..0aadbb1
197 --- /dev/null
198 +++ b/board/freescale/ls1012afrdm/README
199 @@ -0,0 +1,94 @@
200 +Overview
201 +--------
202 +The LS1012AFRDM power supplies (PS) provide all the voltages necessary
203 +for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
204 +and other onboard peripherals.
205 +
206 +LS1012A SoC Overview
207 +--------------------
208 +The LS1012A features an advanced 64-bit ARM v8 Cortex-
209 +A53 processor, with 32 KB of parity protected L1-I cache,
210 +32 KB of ECC protected L1-D cache, as well as 256 KB of
211 +ECC protected L2 cache.
212 +
213 +The LS1012A SoC includes the following function and features:
214 + - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
215 + - ARM v8 cryptography extensions
216 + - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
217 + 16-/8-bit operation (no ECC support)
218 + - ARM core-link CCI-400 cache coherent interconnect
219 + - Packet Forwarding Engine (PFE)
220 + - Cryptography acceleration (SEC)
221 + - Ethernet interfaces supported by PFE:
222 + - One Configurable x3 SerDes:
223 + Two Serdes PLLs supported for usage by any SerDes data lane
224 + Support for up to 6 GBaud operation
225 + - High-speed peripheral interfaces:
226 + - One PCI Express Gen2 controller, supporting x1 operation
227 + - One serial ATA (SATA Gen 3.0) controller
228 + - One USB 3.0/2.0 controller with integrated PHY
229 + - One USB 2.0 controller with ULPI interface. .
230 + - Additional peripheral interfaces:
231 + - One quad serial peripheral interface (QuadSPI) controller
232 + - One serial peripheral interface (SPI) controller
233 + - Two enhanced secure digital host controllers
234 + - Two I2C controllers
235 + - One 16550 compliant DUART (two UART interfaces)
236 + - Two general purpose IOs (GPIO)
237 + - Two FlexTimers
238 + - Five synchronous audio interfaces (SAI)
239 + - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
240 + - Single-source clocking solution enabling generation of core, platform,
241 + DDR, SerDes, and USB clocks from a single external crystal and internal
242 + crystaloscillator
243 + - Thermal monitor unit (TMU) with +/- 3C accuracy
244 + - Two WatchDog timers
245 + - ARM generic timer
246 + - QorIQ platform's trust architecture 2.1
247 +
248 + LS1012AFRDM board Overview
249 + -----------------------
250 + - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
251 + - 2 SGMII 1G PHYs
252 + - DDR Controller
253 + - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
254 + operating at 1.35 V
255 + - QSPI
256 + - Onboard 512 Mbit QSPI flash memory running at speed up
257 + to 108/54 MHz
258 + - One high-speed USB 2.0/3.0 port, one USB 2.0 port
259 + - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
260 + Micro-AB connector.
261 + - USB 2.0 port is a debug port (CMSIS DAP) and is configured
262 + as a Micro-AB device.
263 + - I2C controller
264 + - One I2C bus with connectivity to Arduino headers
265 + - UART
266 + - UART (Console): UART1 (Without flow control) for console
267 + - ARM JTAG support
268 + - ARM Cortex® 10-pin JTAG connector for LS1012A
269 + - CMSIS DAP through K20 microcontroller
270 + - SAI Audio interface
271 + - One SAI port, SAI 2 with full duplex support
272 + - Clocks
273 + - 25 MHz crystal for LS1012A
274 + - 8 MHz Crystal for K20
275 + - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
276 + - Power Supplies
277 + - 5 V input supply from USB
278 + - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
279 + other board interfaces
280 +
281 +Booting Options
282 +---------------
283 +a) QSPI Flash 1
284 +
285 +QSPI flash map
286 +--------------
287 +Images | Size |QSPI Flash Address
288 +------------------------------------------
289 +RCW + PBI | 1MB | 0x4000_0000
290 +U-boot | 1MB | 0x4010_0000
291 +U-boot Env | 1MB | 0x4020_0000
292 +PPA FIT image | 2MB | 0x4050_0000
293 +Linux ITB | ~53MB | 0x40A0_0000
294 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
295 new file mode 100644
296 index 0000000..6be8951
297 --- /dev/null
298 +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
299 @@ -0,0 +1,183 @@
300 +/*
301 + * Copyright 2016 Freescale Semiconductor, Inc.
302 + *
303 + * SPDX-License-Identifier: GPL-2.0+
304 + */
305 +
306 +#include <common.h>
307 +#include <i2c.h>
308 +#include <asm/io.h>
309 +#include <asm/arch/clock.h>
310 +#include <asm/arch/fsl_serdes.h>
311 +#include <asm/arch/ppa.h>
312 +#include <asm/arch/soc.h>
313 +#include <hwconfig.h>
314 +#include <ahci.h>
315 +#include <mmc.h>
316 +#include <scsi.h>
317 +#include <fsl_csu.h>
318 +#include <fsl_esdhc.h>
319 +#include <environment.h>
320 +#include <fsl_mmdc.h>
321 +#include <netdev.h>
322 +
323 +DECLARE_GLOBAL_DATA_PTR;
324 +
325 +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
326 +{
327 + int timeout = 1000;
328 +
329 + out_be32(ptr, value);
330 +
331 + while (in_be32(ptr) & bits) {
332 + udelay(100);
333 + timeout--;
334 + }
335 + if (timeout <= 0)
336 + puts("Error: wait for clear timeout.\n");
337 +}
338 +
339 +int checkboard(void)
340 +{
341 + puts("Board: LS1012AFRDM ");
342 +
343 + return 0;
344 +}
345 +
346 +void mmdc_init(void)
347 +{
348 + struct mmdc_p_regs *mmdc =
349 + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
350 +
351 + /* Set MMDC_MDSCR[CON_REQ] */
352 + out_be32(&mmdc->mdscr, 0x00008000);
353 +
354 + /* configure timing parms */
355 + out_be32(&mmdc->mdotc, 0x12554000);
356 + out_be32(&mmdc->mdcfg0, 0xbabf7954);
357 + out_be32(&mmdc->mdcfg1, 0xff328f64);
358 + out_be32(&mmdc->mdcfg2, 0x01ff00db);
359 +
360 + /* other parms */
361 + out_be32(&mmdc->mdmisc, 0x00000680);
362 + out_be32(&mmdc->mpmur0, 0x00000800);
363 + out_be32(&mmdc->mdrwd, 0x00002000);
364 + out_be32(&mmdc->mpodtctrl, 0x0000022a);
365 +
366 + /* out of reset delays */
367 + out_be32(&mmdc->mdor, 0x00bf1023);
368 +
369 + /* physical parms */
370 + out_be32(&mmdc->mdctl, 0x04180000);
371 + out_be32(&mmdc->mdasp, 0x0000007f);
372 +
373 + /* Enable MMDC */
374 + out_be32(&mmdc->mdctl, 0x84180000);
375 +
376 + /* dram init sequence: update MRs */
377 + out_be32(&mmdc->mdscr, 0x00088032);
378 + out_be32(&mmdc->mdscr, 0x00008033);
379 + out_be32(&mmdc->mdscr, 0x00048031);
380 + out_be32(&mmdc->mdscr, 0x19308030);
381 +
382 + /* dram init sequence: ZQCL */
383 + out_be32(&mmdc->mdscr, 0x04008040);
384 + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
385 +
386 + /* Calibrations now: wr lvl */
387 + out_be32(&mmdc->mdscr, 0x00848031);
388 + out_be32(&mmdc->mdscr, 0x00008200);
389 + set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
390 +
391 + mdelay(1);
392 +
393 + out_be32(&mmdc->mdscr, 0x00048031);
394 + out_be32(&mmdc->mdscr, 0x00008000);
395 +
396 + mdelay(1);
397 +
398 + /* Calibrations now: Read DQS gating calibration */
399 + out_be32(&mmdc->mdscr, 0x04008050);
400 + out_be32(&mmdc->mdscr, 0x00048033);
401 + out_be32(&mmdc->mppdcmpr2, 0x00000001);
402 + out_be32(&mmdc->mprddlctl, 0x40404040);
403 + set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
404 +
405 + out_be32(&mmdc->mdscr, 0x00008033);
406 +
407 + /* Calibrations now: Read calibration */
408 + out_be32(&mmdc->mdscr, 0x04008050);
409 + out_be32(&mmdc->mdscr, 0x00048033);
410 + out_be32(&mmdc->mppdcmpr2, 0x00000001);
411 + set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
412 +
413 + out_be32(&mmdc->mdscr, 0x00008033);
414 +
415 + /* PD, SR */
416 + out_be32(&mmdc->mdpdc, 0x00030035);
417 + out_be32(&mmdc->mapsr, 0x00001067);
418 +
419 + /* refresh scheme */
420 + set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
421 +
422 + /* disable CON_REQ */
423 + out_be32(&mmdc->mdscr, 0x0);
424 +}
425 +
426 +int dram_init(void)
427 +{
428 + mmdc_init();
429 +
430 + gd->ram_size = 0x20000000;
431 +
432 + return 0;
433 +}
434 +
435 +int board_eth_init(bd_t *bis)
436 +{
437 + return pci_eth_init(bis);
438 +}
439 +
440 +int board_early_init_f(void)
441 +{
442 + fsl_lsch2_early_init_f();
443 +
444 + return 0;
445 +}
446 +
447 +int board_init(void)
448 +{
449 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
450 + /*
451 + * Set CCI-400 control override register to enable barrier
452 + * transaction
453 + */
454 + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
455 +
456 +#ifdef CONFIG_ENV_IS_NOWHERE
457 + gd->env_addr = (ulong)&default_environment[0];
458 +#endif
459 +
460 +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
461 + enable_layerscape_ns_access();
462 +#endif
463 +
464 + return 0;
465 +}
466 +
467 +int ft_board_setup(void *blob, bd_t *bd)
468 +{
469 + u64 base[CONFIG_NR_DRAM_BANKS];
470 + u64 size[CONFIG_NR_DRAM_BANKS];
471 +
472 + /* fixup DT for the two DDR banks */
473 + base[0] = gd->bd->bi_dram[0].start;
474 + size[0] = gd->bd->bi_dram[0].size;
475 + base[1] = gd->bd->bi_dram[1].start;
476 + size[1] = gd->bd->bi_dram[1].size;
477 +
478 + fdt_fixup_memory_banks(blob, base, size, 2);
479 + ft_cpu_setup(blob, bd);
480 +
481 + return 0;
482 +}
483 diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
484 new file mode 100644
485 index 0000000..e27181c
486 --- /dev/null
487 +++ b/configs/ls1012afrdm_qspi_defconfig
488 @@ -0,0 +1,10 @@
489 +CONFIG_ARM=y
490 +CONFIG_TARGET_LS1012AFRDM=y
491 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
492 +# CONFIG_CMD_IMLS is not set
493 +CONFIG_SYS_NS16550=y
494 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
495 +CONFIG_OF_CONTROL=y
496 +CONFIG_DM=y
497 +CONFIG_SPI_FLASH=y
498 +CONFIG_DM_SPI=y
499 diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
500 new file mode 100644
501 index 0000000..3231ab7
502 --- /dev/null
503 +++ b/include/configs/ls1012afrdm.h
504 @@ -0,0 +1,59 @@
505 +/*
506 + * Copyright 2016 Freescale Semiconductor, Inc.
507 + *
508 + * SPDX-License-Identifier: GPL-2.0+
509 + */
510 +
511 +#ifndef __LS1012ARDB_H__
512 +#define __LS1012ARDB_H__
513 +
514 +#include "ls1012a_common.h"
515 +
516 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
517 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1
518 +#define CONFIG_NR_DRAM_BANKS 2
519 +
520 +#define CONFIG_CMD_MEMINFO
521 +#define CONFIG_CMD_MEMTEST
522 +#define CONFIG_SYS_MEMTEST_START 0x80000000
523 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
524 +
525 +#define CONFIG_PHYLIB
526 +#define CONFIG_PHY_REALTEK
527 +/*
528 +* USB
529 +*/
530 +#define CONFIG_HAS_FSL_XHCI_USB
531 +
532 +#ifdef CONFIG_HAS_FSL_XHCI_USB
533 +#define CONFIG_USB_XHCI
534 +#define CONFIG_USB_XHCI_FSL
535 +#define CONFIG_USB_XHCI_DWC3
536 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
537 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
538 +#define CONFIG_CMD_USB
539 +#define CONFIG_USB_STORAGE
540 +#define CONFIG_CMD_EXT2
541 +
542 +#define CONFIG_USB_DWC3
543 +#define CONFIG_USB_DWC3_GADGET
544 +
545 +#define CONFIG_USB_GADGET
546 +#define CONFIG_USB_FUNCTION_MASS_STORAGE
547 +#define CONFIG_USB_GADGET_DOWNLOAD
548 +#define CONFIG_USB_GADGET_VBUS_DRAW 2
549 +#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
550 +#define CONFIG_G_DNL_VENDOR_NUM 0x1234
551 +#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
552 +#define CONFIG_USB_GADGET_DUALSPEED
553 +
554 +/* USB Gadget ums command */
555 +#define CONFIG_CMD_USB_MASS_STORAGE
556 +#endif
557 +
558 +#define CONFIG_CMD_MEMINFO
559 +#define CONFIG_CMD_MEMTEST
560 +#define CONFIG_SYS_MEMTEST_START 0x80000000
561 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
562 +
563 +#endif /* __LS1012ARDB_H__ */
564 --
565 1.7.9.5
566
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