layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / package / boot / uboot-layerscape / patches / 0028-fsl-ls1012a-qixis-Add-support-for-qixis-subsystem.patch
1 From 4fcb1d5141ff6d9527ceac9f391e1da4128f5a60 Mon Sep 17 00:00:00 2001
2 From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
3 Date: Tue, 10 May 2016 09:54:36 +0530
4 Subject: [PATCH 28/93] fsl, ls1012a, qixis: Add support for qixis subsystem
5
6 Add support for the printing FPGA build information,
7 altbank switching and board reset using qixis subsystem.
8
9 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
10 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
11 ---
12 board/freescale/ls1012aqds/ls1012aqds.c | 20 +++++++++++++++++++-
13 include/configs/ls1012aqds.h | 17 +++++++++++++++++
14 2 files changed, 36 insertions(+), 1 deletion(-)
15
16 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
17 index 5cb225f..446989b 100644
18 --- a/board/freescale/ls1012aqds/ls1012aqds.c
19 +++ b/board/freescale/ls1012aqds/ls1012aqds.c
20 @@ -44,8 +44,26 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
21
22 int checkboard(void)
23 {
24 - puts("Board: LS1012AQDS\n");
25 + char buf[64];
26 + u8 sw;
27
28 + sw = QIXIS_READ(arch);
29 + printf("Board Arch: V%d, ", sw >> 4);
30 + printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
31 +
32 + sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
33 +
34 + if (sw & QIXIS_LBMAP_ALTBANK)
35 + printf("flash: 2\n");
36 + else
37 + printf("flash: 1\n");
38 +
39 + printf("FPGA: v%d (%s), build %d",
40 + (int)QIXIS_READ(scver), qixis_read_tag(buf),
41 + (int)qixis_read_minor());
42 +
43 + /* the timestamp string contains "\n" at the end */
44 + printf(" on %s", qixis_read_time(buf));
45 return 0;
46 }
47
48 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
49 index 51ca902..de998b8 100644
50 --- a/include/configs/ls1012aqds.h
51 +++ b/include/configs/ls1012aqds.h
52 @@ -26,8 +26,25 @@
53 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
54 #endif
55
56 +/*
57 + * QIXIS Definitions
58 + */
59 +#define CONFIG_FSL_QIXIS
60 +
61 +#ifdef CONFIG_FSL_QIXIS
62 #define CONFIG_QIXIS_I2C_ACCESS
63 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
64 +#define QIXIS_LBMAP_BRDCFG_REG 0x04
65 +#define QIXIS_LBMAP_SWITCH 6
66 +#define QIXIS_LBMAP_MASK 0xf7
67 +#define QIXIS_LBMAP_SHIFT 0
68 +#define QIXIS_LBMAP_DFLTBANK 0x00
69 +#define QIXIS_LBMAP_ALTBANK 0x08
70 +#define QIXIS_RST_CTL_RESET 0x41
71 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
72 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
73 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
74 +#endif
75
76 /*
77 * I2C bus multiplexer
78 --
79 1.7.9.5
80