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layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / package / boot / uboot-layerscape / patches / 0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch
1 From 4bb641f4d28053bd1ff4af73dc0a63be2151f851 Mon Sep 17 00:00:00 2001
2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
3 Date: Mon, 25 Apr 2016 14:37:33 +0530
4 Subject: [PATCH 15/93] armv8: ls1012a: Add support of ls1012ardb board
5
6 QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
7 development platform, with a complete debugging environment.
8 The LS1012ARDB board supports the QorIQ LS1012A processor and is
9 optimized to support the high-bandwidth DDR3L memory and
10 a full complement of high-speed SerDes ports.
11
12 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
13 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
14 ---
15 arch/arm/Kconfig | 10 ++
16 arch/arm/dts/Makefile | 3 +-
17 arch/arm/dts/fsl-ls1012a-rdb.dts | 16 +++
18 arch/arm/dts/fsl-ls1012a-rdb.dtsi | 39 ++++++
19 board/freescale/ls1012ardb/Kconfig | 15 +++
20 board/freescale/ls1012ardb/MAINTAINERS | 6 +
21 board/freescale/ls1012ardb/Makefile | 7 +
22 board/freescale/ls1012ardb/README | 89 +++++++++++++
23 board/freescale/ls1012ardb/ls1012ardb.c | 220 +++++++++++++++++++++++++++++++
24 configs/ls1012ardb_qspi_defconfig | 10 ++
25 include/configs/ls1012a_common.h | 3 +-
26 include/configs/ls1012ardb.h | 61 +++++++++
27 include/linux/usb/xhci-fsl.h | 2 +-
28 13 files changed, 477 insertions(+), 4 deletions(-)
29 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
30 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
31 create mode 100644 board/freescale/ls1012ardb/Kconfig
32 create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
33 create mode 100644 board/freescale/ls1012ardb/Makefile
34 create mode 100644 board/freescale/ls1012ardb/README
35 create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
36 create mode 100644 configs/ls1012ardb_qspi_defconfig
37 create mode 100644 include/configs/ls1012ardb.h
38
39 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
40 index f5033db..5c20801 100644
41 --- a/arch/arm/Kconfig
42 +++ b/arch/arm/Kconfig
43 @@ -656,6 +656,15 @@ config TARGET_LS1012AQDS
44 development platform that supports the QorIQ LS1012A
45 Layerscape Architecture processor.
46
47 +config TARGET_LS1012ARDB
48 + bool "Support ls1012ardb"
49 + select ARM64
50 + help
51 + Support for Freescale LS1012ARDB platform.
52 + The LS1012A Reference design board (RDB) is a high-performance
53 + development platform that supports the QorIQ LS1012A
54 + Layerscape Architecture processor.
55 +
56 config TARGET_LS1021AQDS
57 bool "Support ls1021aqds"
58 select CPU_V7
59 @@ -802,6 +811,7 @@ source "board/freescale/ls1043aqds/Kconfig"
60 source "board/freescale/ls1021atwr/Kconfig"
61 source "board/freescale/ls1043ardb/Kconfig"
62 source "board/freescale/ls1012aqds/Kconfig"
63 +source "board/freescale/ls1012ardb/Kconfig"
64 source "board/freescale/mx23evk/Kconfig"
65 source "board/freescale/mx25pdk/Kconfig"
66 source "board/freescale/mx28evk/Kconfig"
67 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
68 index ed5eb38..9e8137b 100644
69 --- a/arch/arm/dts/Makefile
70 +++ b/arch/arm/dts/Makefile
71 @@ -95,7 +95,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
72 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
73 fsl-ls1043a-qds-lpuart.dtb \
74 fsl-ls1043a-rdb.dtb \
75 - fsl-ls1012a-qds.dtb
76 + fsl-ls1012a-qds.dtb \
77 + fsl-ls1012a-rdb.dtb
78
79 dtb-$(CONFIG_MACH_SUN4I) += \
80 sun4i-a10-a1000.dtb \
81 diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
82 new file mode 100644
83 index 0000000..4ec9786
84 --- /dev/null
85 +++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
86 @@ -0,0 +1,16 @@
87 +/*
88 + * Device Tree file for Freescale Layerscape-1012A family SoC.
89 + *
90 + * Copyright (C) 2016, Freescale Semiconductor
91 + *
92 + * SPDX-License-Identifier: GPL-2.0+
93 + */
94 +
95 +/dts-v1/;
96 +#include "fsl-ls1012a-rdb.dtsi"
97 +
98 +/ {
99 + chosen {
100 + stdout-path = &duart0;
101 + };
102 +};
103 diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
104 new file mode 100644
105 index 0000000..71aba78
106 --- /dev/null
107 +++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
108 @@ -0,0 +1,39 @@
109 +/*
110 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
111 + *
112 + * Copyright (C) 2016, Freescale Semiconductor
113 + *
114 + * This file is licensed under the terms of the GNU General Public
115 + * License version 2. This program is licensed "as is" without any
116 + * warranty of any kind, whether express or implied.
117 + */
118 +
119 +/include/ "fsl-ls1012a.dtsi"
120 +
121 +/ {
122 + model = "LS1012A RDB Board";
123 + aliases {
124 + spi0 = &qspi;
125 + };
126 +};
127 +
128 +&qspi {
129 + bus-num = <0>;
130 + status = "okay";
131 +
132 + qflash0: s25fl128s@0 {
133 + #address-cells = <1>;
134 + #size-cells = <1>;
135 + compatible = "spi-flash";
136 + spi-max-frequency = <20000000>;
137 + reg = <0>;
138 + };
139 +};
140 +
141 +&i2c0 {
142 + status = "okay";
143 +};
144 +
145 +&duart0 {
146 + status = "okay";
147 +};
148 diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
149 new file mode 100644
150 index 0000000..3f67c28
151 --- /dev/null
152 +++ b/board/freescale/ls1012ardb/Kconfig
153 @@ -0,0 +1,15 @@
154 +if TARGET_LS1012ARDB
155 +
156 +config SYS_BOARD
157 + default "ls1012ardb"
158 +
159 +config SYS_VENDOR
160 + default "freescale"
161 +
162 +config SYS_SOC
163 + default "fsl-layerscape"
164 +
165 +config SYS_CONFIG_NAME
166 + default "ls1012ardb"
167 +
168 +endif
169 diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
170 new file mode 100644
171 index 0000000..757e810
172 --- /dev/null
173 +++ b/board/freescale/ls1012ardb/MAINTAINERS
174 @@ -0,0 +1,6 @@
175 +LS1012ARDB BOARD
176 +M:
177 +S: Maintained
178 +F: board/freescale/ls1012ardb/
179 +F: include/configs/ls1012ardb.h
180 +F: configs/ls1012ardb_defconfig
181 diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
182 new file mode 100644
183 index 0000000..05fa9d9
184 --- /dev/null
185 +++ b/board/freescale/ls1012ardb/Makefile
186 @@ -0,0 +1,7 @@
187 +#
188 +# Copyright 2016 Freescale Semiconductor, Inc.
189 +#
190 +# SPDX-License-Identifier: GPL-2.0+
191 +#
192 +
193 +obj-y += ls1012ardb.o
194 diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
195 new file mode 100644
196 index 0000000..cda03f6
197 --- /dev/null
198 +++ b/board/freescale/ls1012ardb/README
199 @@ -0,0 +1,89 @@
200 +Overview
201 +--------
202 +The LS1012ARDB power supplies (PS) provide all the voltages necessary
203 +for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
204 +and other onboard peripherals.
205 +
206 +LS1012A SoC Overview
207 +--------------------
208 +The LS1012A features an advanced 64-bit ARM v8 Cortex-
209 +A53 processor, with 32 KB of parity protected L1-I cache,
210 +32 KB of ECC protected L1-D cache, as well as 256 KB of
211 +ECC protected L2 cache.
212 +
213 +The LS1012A SoC includes the following function and features:
214 + - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
215 + - ARM v8 cryptography extensions
216 + - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
217 + 16-/8-bit operation (no ECC support)
218 + - ARM core-link CCI-400 cache coherent interconnect
219 + - Packet Forwarding Engine (PFE)
220 + - Cryptography acceleration (SEC)
221 + - Ethernet interfaces supported by PFE:
222 + - One Configurable x3 SerDes:
223 + Two Serdes PLLs supported for usage by any SerDes data lane
224 + Support for up to 6 GBaud operation
225 + - High-speed peripheral interfaces:
226 + - One PCI Express Gen2 controller, supporting x1 operation
227 + - One serial ATA (SATA Gen 3.0) controller
228 + - One USB 3.0/2.0 controller with integrated PHY
229 + - One USB 2.0 controller with ULPI interface. .
230 + - Additional peripheral interfaces:
231 + - One quad serial peripheral interface (QuadSPI) controller
232 + - One serial peripheral interface (SPI) controller
233 + - Two enhanced secure digital host controllers
234 + - Two I2C controllers
235 + - One 16550 compliant DUART (two UART interfaces)
236 + - Two general purpose IOs (GPIO)
237 + - Two FlexTimers
238 + - Five synchronous audio interfaces (SAI)
239 + - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
240 + - Single-source clocking solution enabling generation of core, platform,
241 + DDR, SerDes, and USB clocks from a single external crystal and internal
242 + crystaloscillator
243 + - Thermal monitor unit (TMU) with +/- 3C accuracy
244 + - Two WatchDog timers
245 + - ARM generic timer
246 + - QorIQ platform's trust architecture 2.1
247 +
248 + LS1012ARDB board Overview
249 + -----------------------
250 + - SERDES Connections, 4 lanes supporting:
251 + - PCI Express - 3.0
252 + - SGMII, SGMII 2.5
253 + - SATA 3.0
254 + - DDR Controller
255 + - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
256 + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
257 + signals to
258 + - QSPI NOR flash memory (2 virtual banks)
259 + - the QSPI emulator.s
260 + - USB 3.0
261 + - one high-speed USB 2.0/3.0 port.
262 + - Two enhanced secure digital host controllers:
263 + - SDHC1 controller can be connected to onboard SDHC connector
264 + - SDHC2 controller: Three dual 1:4 mux/demux devices,
265 + 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
266 + SDIO WiFi, SPI, and Ardiuno shield
267 + - 2 I2C controllers
268 + - One SATA onboard connectors
269 + - UART
270 + - The LS1012A processor consists of two UART controllers,
271 + out of which only UART1 is used on RDB.
272 + - ARM JTAG support
273 +
274 +Booting Options
275 +---------------
276 +a) QSPI Flash Emu Boot
277 +b) QSPI Flash 1
278 +c) QSPI Flash 2
279 +
280 +QSPI flash map
281 +--------------
282 +Images | Size |QSPI Flash Address
283 +------------------------------------------
284 +RCW + PBI | 1MB | 0x4000_0000
285 +U-boot | 1MB | 0x4010_0000
286 +U-boot Env | 1MB | 0x4020_0000
287 +PPA FIT image | 2MB | 0x4050_0000
288 +Linux ITB | ~53MB | 0x40A0_0000
289 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
290 new file mode 100644
291 index 0000000..4a7aaaa
292 --- /dev/null
293 +++ b/board/freescale/ls1012ardb/ls1012ardb.c
294 @@ -0,0 +1,220 @@
295 +/*
296 + * Copyright 2016 Freescale Semiconductor, Inc.
297 + *
298 + * SPDX-License-Identifier: GPL-2.0+
299 + */
300 +
301 +#include <common.h>
302 +#include <i2c.h>
303 +#include <asm/io.h>
304 +#include <asm/arch/clock.h>
305 +#include <asm/arch/fsl_serdes.h>
306 +#include <asm/arch/ppa.h>
307 +#include <asm/arch/soc.h>
308 +#include <hwconfig.h>
309 +#include <ahci.h>
310 +#include <mmc.h>
311 +#include <scsi.h>
312 +#include <fsl_csu.h>
313 +#include <fsl_esdhc.h>
314 +#include <environment.h>
315 +#include <fsl_mmdc.h>
316 +#include <netdev.h>
317 +
318 +DECLARE_GLOBAL_DATA_PTR;
319 +
320 +int checkboard(void)
321 +{
322 + u8 in1;
323 +
324 + puts("Board: LS1012ARDB ");
325 +
326 + /* Initialize i2c early for Serial flash bank information */
327 + i2c_set_bus_num(0);
328 +
329 + if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
330 + printf("Error reading i2c boot information!\n");
331 + return 0; /* Don't want to hang() on this error */
332 + }
333 +
334 + puts("Version");
335 + if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
336 + puts(": RevA");
337 + else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
338 + puts(": RevB");
339 + else
340 + puts(": unknown");
341 +
342 + printf(", boot from QSPI");
343 + if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
344 + puts(": emu\n");
345 + else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
346 + puts(": bank1\n");
347 + else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
348 + puts(": bank2\n");
349 + else
350 + puts("unknown\n");
351 +
352 + return 0;
353 +}
354 +
355 +void mmdc_init(void)
356 +{
357 + struct mmdc_p_regs *mmdc =
358 + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
359 +
360 + /* Set MMDC_MDSCR[CON_REQ] */
361 + out_be32(&mmdc->mdscr, 0x00008000);
362 +
363 + /* configure timing parms */
364 + out_be32(&mmdc->mdotc, 0x12554000);
365 + out_be32(&mmdc->mdcfg0, 0xbabf7954);
366 + out_be32(&mmdc->mdcfg1, 0xff328f64);
367 + out_be32(&mmdc->mdcfg2, 0x01ff00db);
368 +
369 + /* other parms */
370 + out_be32(&mmdc->mdmisc, 0x00000680);
371 + out_be32(&mmdc->mpmur0, 0x00000800);
372 + out_be32(&mmdc->mdrwd, 0x00002000);
373 + out_be32(&mmdc->mpodtctrl, 0x0000022a);
374 +
375 + /* out of reset delays */
376 + out_be32(&mmdc->mdor, 0x00bf1023);
377 +
378 + /* physical parms */
379 + out_be32(&mmdc->mdctl, 0x05180000);
380 + out_be32(&mmdc->mdasp, 0x0000007f);
381 +
382 + /* Enable MMDC */
383 + out_be32(&mmdc->mdctl, 0x85180000);
384 +
385 + /* dram init sequence: update MRs */
386 + out_be32(&mmdc->mdscr, 0x00088032);
387 + out_be32(&mmdc->mdscr, 0x00008033);
388 + out_be32(&mmdc->mdscr, 0x00048031);
389 + out_be32(&mmdc->mdscr, 0x19308030);
390 +
391 + /* dram init sequence: ZQCL */
392 + out_be32(&mmdc->mdscr, 0x04008040);
393 + out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
394 +
395 + mdelay(100);
396 +
397 + /* Calibrations now: wr lvl */
398 + out_be32(&mmdc->mdscr, 0x00848031);
399 + out_be32(&mmdc->mdscr, 0x00008200);
400 + out_be32(&mmdc->mpwlgcr, 0x00000001);
401 +
402 + mdelay(100);
403 +
404 + out_be32(&mmdc->mdscr, 0x00048031);
405 + out_be32(&mmdc->mdscr, 0x00008000);
406 +
407 + /* manual_refresh */
408 + out_be32(&mmdc->mdscr, 0x00008020);
409 +
410 + mdelay(100);
411 +
412 + /* Calibrations now: Read DQS gating calibration */
413 + out_be32(&mmdc->mdscr, 0x04008050);
414 + out_be32(&mmdc->mdscr, 0x00048033);
415 + out_be32(&mmdc->mppdcmpr2, 0x00000001);
416 + out_be32(&mmdc->mprddlctl, 0x40404040);
417 + out_be32(&mmdc->mpdgctrl0, 0x10000000);
418 +
419 + mdelay(100);
420 +
421 + out_be32(&mmdc->mdscr, 0x00008033);
422 +
423 + /* manual_refresh */
424 + out_be32(&mmdc->mdscr, 0x00008020);
425 +
426 + mdelay(100);
427 +
428 + /* Calibrations now: Read calibration */
429 + out_be32(&mmdc->mdscr, 0x04008050);
430 + out_be32(&mmdc->mdscr, 0x00048033);
431 + out_be32(&mmdc->mppdcmpr2, 0x00000001);
432 + out_be32(&mmdc->mprddlhwctl, 0x00000010);
433 +
434 + mdelay(400);
435 +
436 + out_be32(&mmdc->mdscr, 0x00008033);
437 +
438 + /* manual_refresh */
439 + out_be32(&mmdc->mdscr, 0x00008020);
440 +
441 + mdelay(100);
442 +
443 + /* PD, SR */
444 + out_be32(&mmdc->mdpdc, 0x00030035);
445 + out_be32(&mmdc->mapsr, 0x00001067);
446 +
447 + /* refresh scheme */
448 + out_be32(&mmdc->mdref, 0x103e8000);
449 +
450 + mdelay(400);
451 +
452 + /* disable CON_REQ */
453 + out_be32(&mmdc->mdscr, 0x0);
454 +
455 + mdelay(50);
456 +}
457 +
458 +int dram_init(void)
459 +{
460 + mmdc_init();
461 +
462 + gd->ram_size = 0x40000000;
463 +
464 + return 0;
465 +}
466 +
467 +int board_eth_init(bd_t *bis)
468 +{
469 + return pci_eth_init(bis);
470 +}
471 +
472 +int board_early_init_f(void)
473 +{
474 + fsl_lsch2_early_init_f();
475 +
476 + return 0;
477 +}
478 +
479 +int board_init(void)
480 +{
481 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
482 + /*
483 + * Set CCI-400 control override register to enable barrier
484 + * transaction
485 + */
486 + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
487 +
488 +#ifdef CONFIG_ENV_IS_NOWHERE
489 + gd->env_addr = (ulong)&default_environment[0];
490 +#endif
491 +
492 +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
493 + enable_layerscape_ns_access();
494 +#endif
495 +
496 + return 0;
497 +}
498 +
499 +int ft_board_setup(void *blob, bd_t *bd)
500 +{
501 + u64 base[CONFIG_NR_DRAM_BANKS];
502 + u64 size[CONFIG_NR_DRAM_BANKS];
503 +
504 + /* fixup DT for the two DDR banks */
505 + base[0] = gd->bd->bi_dram[0].start;
506 + size[0] = gd->bd->bi_dram[0].size;
507 + base[1] = gd->bd->bi_dram[1].start;
508 + size[1] = gd->bd->bi_dram[1].size;
509 +
510 + fdt_fixup_memory_banks(blob, base, size, 2);
511 + ft_cpu_setup(blob, bd);
512 +
513 + return 0;
514 +}
515 diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
516 new file mode 100644
517 index 0000000..f819038
518 --- /dev/null
519 +++ b/configs/ls1012ardb_qspi_defconfig
520 @@ -0,0 +1,10 @@
521 +CONFIG_ARM=y
522 +CONFIG_TARGET_LS1012ARDB=y
523 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
524 +# CONFIG_CMD_IMLS is not set
525 +CONFIG_SYS_NS16550=y
526 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
527 +CONFIG_OF_CONTROL=y
528 +CONFIG_DM=y
529 +CONFIG_SPI_FLASH=y
530 +CONFIG_DM_SPI=y
531 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
532 index 9ed04f9..3fd360a 100644
533 --- a/include/configs/ls1012a_common.h
534 +++ b/include/configs/ls1012a_common.h
535 @@ -12,7 +12,7 @@
536 #define CONFIG_LS1012A
537 #define CONFIG_GICV2
538
539 -#define CONFIG_SYS_HAS_SERDES
540 +#define CONFIG_SYS_HAS_SERDES
541
542 #include <asm/arch/config.h>
543 #define CONFIG_SYS_NO_FLASH
544 @@ -56,7 +56,6 @@
545 #define CONFIG_ENV_SPI_MODE 0x03
546 #define CONFIG_CMD_SF
547 #define CONFIG_SPI_FLASH_SPANSION
548 -#define CONFIG_SPI_FLASH_ATMEL
549 #define CONFIG_FSL_SPI_INTERFACE
550 #define CONFIG_SF_DATAFLASH
551
552 diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
553 new file mode 100644
554 index 0000000..9ff5935
555 --- /dev/null
556 +++ b/include/configs/ls1012ardb.h
557 @@ -0,0 +1,61 @@
558 +/*
559 + * Copyright 2016 Freescale Semiconductor, Inc.
560 + *
561 + * SPDX-License-Identifier: GPL-2.0+
562 + */
563 +
564 +#ifndef __LS1012ARDB_H__
565 +#define __LS1012ARDB_H__
566 +
567 +#include "ls1012a_common.h"
568 +
569 +
570 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
571 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1
572 +#define CONFIG_NR_DRAM_BANKS 2
573 +
574 +#define CONFIG_CMD_MEMINFO
575 +#define CONFIG_CMD_MEMTEST
576 +#define CONFIG_SYS_MEMTEST_START 0x80000000
577 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
578 +
579 +#define CONFIG_PHYLIB
580 +#define CONFIG_PHY_REALTEK
581 +#define SGMII_PHY1_ADDR 0x0
582 +#define RGMII_PHY2_ADDR 0x1
583 +
584 +/*
585 +* USB
586 +*/
587 +#define CONFIG_HAS_FSL_XHCI_USB
588 +
589 +#ifdef CONFIG_HAS_FSL_XHCI_USB
590 +#define CONFIG_USB_XHCI
591 +#define CONFIG_USB_XHCI_FSL
592 +#define CONFIG_USB_XHCI_DWC3
593 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
594 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
595 +#define CONFIG_CMD_USB
596 +#define CONFIG_USB_STORAGE
597 +#define CONFIG_CMD_EXT2
598 +#endif
599 +
600 +/*
601 + * I2C IO expander
602 + */
603 +
604 +#define I2C_MUX_IO1_ADDR 0x24
605 +#define __SW_BOOT_MASK 0xFC
606 +#define __SW_BOOT_EMU 0x10
607 +#define __SW_BOOT_BANK1 0x00
608 +#define __SW_BOOT_BANK2 0x01
609 +#define __SW_REV_MASK 0x07
610 +#define __SW_REV_A 0xF8
611 +#define __SW_REV_B 0xF0
612 +
613 +#define CONFIG_CMD_MEMINFO
614 +#define CONFIG_CMD_MEMTEST
615 +#define CONFIG_SYS_MEMTEST_START 0x80000000
616 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
617 +
618 +#endif /* __LS1012ARDB_H__ */
619 diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
620 index 72a5d5b..7ab88c3 100644
621 --- a/include/linux/usb/xhci-fsl.h
622 +++ b/include/linux/usb/xhci-fsl.h
623 @@ -62,7 +62,7 @@ struct fsl_xhci {
624 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
625 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
626 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
627 -#elif defined(CONFIG_LS1043A)
628 +#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
629 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
630 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
631 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
632 --
633 1.7.9.5
634
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