projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / package / boot / uboot-layerscape / patches / 0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch
1 From faf0aac702a2253471f98687ed40138e514e38ab Mon Sep 17 00:00:00 2001
2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
3 Date: Mon, 25 Apr 2016 14:36:16 +0530
4 Subject: [PATCH 14/93] armv8: ls1012a: Add support of ls1012aqds board
5
6 QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
7 development platform, with a complete debugging environment.
8 The LS1012AQDS board supports the QorIQ LS1012A processor and is
9 optimized to support the high-bandwidth DDR3L memory and
10 a full complement of high-speed SerDes ports.
11
12 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
13 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
14 ---
15 arch/arm/Kconfig | 10 ++
16 arch/arm/dts/Makefile | 3 +-
17 arch/arm/dts/fsl-ls1012a-qds.dts | 14 ++
18 arch/arm/dts/fsl-ls1012a-qds.dtsi | 123 +++++++++++++
19 arch/arm/dts/fsl-ls1012a.dtsi | 119 ++++++++++++
20 board/freescale/ls1012aqds/Kconfig | 15 ++
21 board/freescale/ls1012aqds/MAINTAINERS | 6 +
22 board/freescale/ls1012aqds/Makefile | 7 +
23 board/freescale/ls1012aqds/README | 94 ++++++++++
24 board/freescale/ls1012aqds/ls1012aqds.c | 199 ++++++++++++++++++++
25 board/freescale/ls1012aqds/ls1012aqds_qixis.h | 35 ++++
26 configs/ls1012aqds_qspi_defconfig | 10 ++
27 include/configs/ls1012a_common.h | 239 +++++++++++++++++++++++++
28 include/configs/ls1012aqds.h | 133 ++++++++++++++
29 include/fsl_mmdc.h | 57 +++++-
30 15 files changed, 1055 insertions(+), 9 deletions(-)
31 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts
32 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi
33 create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi
34 create mode 100644 board/freescale/ls1012aqds/Kconfig
35 create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
36 create mode 100644 board/freescale/ls1012aqds/Makefile
37 create mode 100644 board/freescale/ls1012aqds/README
38 create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
39 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
40 create mode 100644 configs/ls1012aqds_qspi_defconfig
41 create mode 100644 include/configs/ls1012a_common.h
42 create mode 100644 include/configs/ls1012aqds.h
43
44 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
45 index 9bd6cf1..f5033db 100644
46 --- a/arch/arm/Kconfig
47 +++ b/arch/arm/Kconfig
48 @@ -647,6 +647,15 @@ config TARGET_HIKEY
49 Support for HiKey 96boards platform. It features a HI6220
50 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
51
52 +config TARGET_LS1012AQDS
53 + bool "Support ls1012aqds"
54 + select ARM64
55 + help
56 + Support for Freescale LS1012AQDS platform.
57 + The LS1012A Development System (QDS) is a high-performance
58 + development platform that supports the QorIQ LS1012A
59 + Layerscape Architecture processor.
60 +
61 config TARGET_LS1021AQDS
62 bool "Support ls1021aqds"
63 select CPU_V7
64 @@ -792,6 +801,7 @@ source "board/freescale/ls1021aqds/Kconfig"
65 source "board/freescale/ls1043aqds/Kconfig"
66 source "board/freescale/ls1021atwr/Kconfig"
67 source "board/freescale/ls1043ardb/Kconfig"
68 +source "board/freescale/ls1012aqds/Kconfig"
69 source "board/freescale/mx23evk/Kconfig"
70 source "board/freescale/mx25pdk/Kconfig"
71 source "board/freescale/mx28evk/Kconfig"
72 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
73 index c1c81e4..ed5eb38 100644
74 --- a/arch/arm/dts/Makefile
75 +++ b/arch/arm/dts/Makefile
76 @@ -94,7 +94,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
77 fsl-ls2080a-rdb.dtb
78 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
79 fsl-ls1043a-qds-lpuart.dtb \
80 - fsl-ls1043a-rdb.dtb
81 + fsl-ls1043a-rdb.dtb \
82 + fsl-ls1012a-qds.dtb
83
84 dtb-$(CONFIG_MACH_SUN4I) += \
85 sun4i-a10-a1000.dtb \
86 diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
87 new file mode 100644
88 index 0000000..ef6de34
89 --- /dev/null
90 +++ b/arch/arm/dts/fsl-ls1012a-qds.dts
91 @@ -0,0 +1,14 @@
92 +/*
93 + * Copyright (C) 2016 Freescale Semiconductor
94 + *
95 + * SPDX-License-Identifier: GPL-2.0+
96 + */
97 +
98 +/dts-v1/;
99 +#include "fsl-ls1012a-qds.dtsi"
100 +
101 +/ {
102 + chosen {
103 + stdout-path = &duart0;
104 + };
105 +};
106 diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
107 new file mode 100644
108 index 0000000..a32a84a
109 --- /dev/null
110 +++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
111 @@ -0,0 +1,123 @@
112 +/*
113 + * Copyright (C) 2016 Freescale Semiconductor
114 + *
115 + * SPDX-License-Identifier: GPL-2.0+
116 + */
117 +
118 +/include/ "fsl-ls1012a.dtsi"
119 +
120 +/ {
121 + model = "LS1012A QDS Board";
122 + aliases {
123 + spi0 = &qspi;
124 + spi1 = &dspi0;
125 + };
126 +};
127 +
128 +&dspi0 {
129 + bus-num = <0>;
130 + status = "okay";
131 +
132 + dflash0: n25q128a {
133 + #address-cells = <1>;
134 + #size-cells = <1>;
135 + compatible = "spi-flash";
136 + reg = <0>;
137 + spi-max-frequency = <1000000>; /* input clock */
138 + };
139 +
140 + dflash1: sst25wf040b {
141 + #address-cells = <1>;
142 + #size-cells = <1>;
143 + compatible = "spi-flash";
144 + spi-max-frequency = <3500000>;
145 + reg = <1>;
146 + };
147 +
148 + dflash2: en25s64 {
149 + #address-cells = <1>;
150 + #size-cells = <1>;
151 + compatible = "spi-flash";
152 + spi-max-frequency = <3500000>;
153 + reg = <2>;
154 + };
155 +};
156 +
157 +&qspi {
158 + bus-num = <0>;
159 + status = "okay";
160 +
161 + qflash0: s25fl128s@0 {
162 + #address-cells = <1>;
163 + #size-cells = <1>;
164 + compatible = "spi-flash";
165 + spi-max-frequency = <20000000>;
166 + reg = <0>;
167 + };
168 +};
169 +
170 +&i2c0 {
171 + status = "okay";
172 + pca9547@77 {
173 + compatible = "philips,pca9547";
174 + reg = <0x77>;
175 + #address-cells = <1>;
176 + #size-cells = <0>;
177 +
178 + i2c@0 {
179 + #address-cells = <1>;
180 + #size-cells = <0>;
181 + reg = <0x0>;
182 +
183 + rtc@68 {
184 + compatible = "dallas,ds3232";
185 + reg = <0x68>;
186 + /* IRQ10_B */
187 + interrupts = <0 150 0x4>;
188 + };
189 + };
190 +
191 + i2c@2 {
192 + #address-cells = <1>;
193 + #size-cells = <0>;
194 + reg = <0x2>;
195 +
196 + ina220@40 {
197 + compatible = "ti,ina220";
198 + reg = <0x40>;
199 + shunt-resistor = <1000>;
200 + };
201 +
202 + ina220@41 {
203 + compatible = "ti,ina220";
204 + reg = <0x41>;
205 + shunt-resistor = <1000>;
206 + };
207 + };
208 +
209 + i2c@3 {
210 + #address-cells = <1>;
211 + #size-cells = <0>;
212 + reg = <0x3>;
213 +
214 + eeprom@56 {
215 + compatible = "at24,24c512";
216 + reg = <0x56>;
217 + };
218 +
219 + eeprom@57 {
220 + compatible = "at24,24c512";
221 + reg = <0x57>;
222 + };
223 +
224 + adt7461a@4c {
225 + compatible = "adt7461a";
226 + reg = <0x4c>;
227 + };
228 + };
229 + };
230 +};
231 +
232 +&duart0 {
233 + status = "okay";
234 +};
235 diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
236 new file mode 100644
237 index 0000000..87a287a
238 --- /dev/null
239 +++ b/arch/arm/dts/fsl-ls1012a.dtsi
240 @@ -0,0 +1,119 @@
241 +/*
242 + * Copyright (C) 2016 Freescale Semiconductor
243 + *
244 + * SPDX-License-Identifier: GPL-2.0+
245 + */
246 +
247 +/include/ "skeleton64.dtsi"
248 +
249 +/ {
250 + compatible = "fsl,ls1012a";
251 + interrupt-parent = <&gic>;
252 + cpus {
253 + #address-cells = <2>;
254 + #size-cells = <0>;
255 +
256 + cpu0: cpu@0 {
257 + device_type = "cpu";
258 + compatible = "arm,cortex-a53";
259 + reg = <0x0 0x0>;
260 + clocks = <&clockgen 1 0>;
261 + };
262 +
263 + };
264 +
265 + sysclk: sysclk {
266 + compatible = "fixed-clock";
267 + #clock-cells = <0>;
268 + clock-frequency = <100000000>;
269 + clock-output-names = "sysclk";
270 + };
271 +
272 + gic: interrupt-controller@1400000 {
273 + compatible = "arm,gic-400";
274 + #interrupt-cells = <3>;
275 + interrupt-controller;
276 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
277 + <0x0 0x1402000 0 0x2000>, /* GICC */
278 + <0x0 0x1404000 0 0x2000>, /* GICH */
279 + <0x0 0x1406000 0 0x2000>; /* GICV */
280 + interrupts = <1 9 0xf08>;
281 + };
282 +
283 + soc {
284 + compatible = "simple-bus";
285 + #address-cells = <2>;
286 + #size-cells = <2>;
287 + ranges;
288 +
289 + clockgen: clocking@1ee1000 {
290 + compatible = "fsl,ls1012a-clockgen";
291 + reg = <0x0 0x1ee1000 0x0 0x1000>;
292 + #clock-cells = <2>;
293 + clocks = <&sysclk>;
294 + };
295 +
296 + dspi0: dspi@2100000 {
297 + compatible = "fsl,vf610-dspi";
298 + #address-cells = <1>;
299 + #size-cells = <0>;
300 + reg = <0x0 0x2100000 0x0 0x10000>;
301 + interrupts = <0 64 0x4>;
302 + clock-names = "dspi";
303 + clocks = <&clockgen 4 0>;
304 + num-cs = <6>;
305 + big-endian;
306 + status = "disabled";
307 + };
308 +
309 +
310 + i2c0: i2c@2180000 {
311 + compatible = "fsl,vf610-i2c";
312 + #address-cells = <1>;
313 + #size-cells = <0>;
314 + reg = <0x0 0x2180000 0x0 0x10000>;
315 + interrupts = <0 56 0x4>;
316 + clock-names = "i2c";
317 + clocks = <&clockgen 4 0>;
318 + status = "disabled";
319 + };
320 +
321 + i2c1: i2c@2190000 {
322 + compatible = "fsl,vf610-i2c";
323 + #address-cells = <1>;
324 + #size-cells = <0>;
325 + reg = <0x0 0x2190000 0x0 0x10000>;
326 + interrupts = <0 57 0x4>;
327 + clock-names = "i2c";
328 + clocks = <&clockgen 4 0>;
329 + status = "disabled";
330 + };
331 +
332 + duart0: serial@21c0500 {
333 + compatible = "fsl,ns16550", "ns16550a";
334 + reg = <0x00 0x21c0500 0x0 0x100>;
335 + interrupts = <0 54 0x4>;
336 + clocks = <&clockgen 4 0>;
337 + };
338 +
339 + duart1: serial@21c0600 {
340 + compatible = "fsl,ns16550", "ns16550a";
341 + reg = <0x00 0x21c0600 0x0 0x100>;
342 + interrupts = <0 54 0x4>;
343 + clocks = <&clockgen 4 0>;
344 + };
345 +
346 + qspi: quadspi@1550000 {
347 + compatible = "fsl,vf610-qspi";
348 + #address-cells = <1>;
349 + #size-cells = <0>;
350 + reg = <0x0 0x1550000 0x0 0x10000>,
351 + <0x0 0x40000000 0x0 0x4000000>;
352 + reg-names = "QuadSPI", "QuadSPI-memory";
353 + num-cs = <2>;
354 + big-endian;
355 + status = "disabled";
356 + };
357 +
358 + };
359 +};
360 diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
361 new file mode 100644
362 index 0000000..1257ec8
363 --- /dev/null
364 +++ b/board/freescale/ls1012aqds/Kconfig
365 @@ -0,0 +1,15 @@
366 +if TARGET_LS1012AQDS
367 +
368 +config SYS_BOARD
369 + default "ls1012aqds"
370 +
371 +config SYS_VENDOR
372 + default "freescale"
373 +
374 +config SYS_SOC
375 + default "fsl-layerscape"
376 +
377 +config SYS_CONFIG_NAME
378 + default "ls1012aqds"
379 +
380 +endif
381 diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
382 new file mode 100644
383 index 0000000..3c01df6
384 --- /dev/null
385 +++ b/board/freescale/ls1012aqds/MAINTAINERS
386 @@ -0,0 +1,6 @@
387 +LS1012AQDS BOARD
388 +M:
389 +S: Maintained
390 +F: board/freescale/ls1012aqds/
391 +F: include/configs/ls1012aqds.h
392 +F: configs/ls1012aqds_defconfig
393 diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
394 new file mode 100644
395 index 0000000..0b813f9
396 --- /dev/null
397 +++ b/board/freescale/ls1012aqds/Makefile
398 @@ -0,0 +1,7 @@
399 +#
400 +# Copyright 2016 Freescale Semiconductor, Inc.
401 +#
402 +# SPDX-License-Identifier: GPL-2.0+
403 +#
404 +
405 +obj-y += ls1012aqds.o
406 diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
407 new file mode 100644
408 index 0000000..e94a267
409 --- /dev/null
410 +++ b/board/freescale/ls1012aqds/README
411 @@ -0,0 +1,94 @@
412 +Overview
413 +--------
414 +The LS1012AQDS power supplies (PS) provide all the voltages necessary
415 +for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
416 +and other onboard peripherals.
417 +
418 +LS1012A SoC Overview
419 +--------------------
420 +The LS1012A features an advanced 64-bit ARM v8 Cortex-
421 +A53 processor, with 32 KB of parity protected L1-I cache,
422 +32 KB of ECC protected L1-D cache, as well as 256 KB of
423 +ECC protected L2 cache.
424 +
425 +The LS1012A SoC includes the following function and features:
426 + - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
427 + - ARM v8 cryptography extensions
428 + - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
429 + 16-/8-bit operation (no ECC support)
430 + - ARM core-link CCI-400 cache coherent interconnect
431 + - Packet Forwarding Engine (PFE)
432 + - Cryptography acceleration (SEC)
433 + - Ethernet interfaces supported by PFE:
434 + - One Configurable x3 SerDes:
435 + Two Serdes PLLs supported for usage by any SerDes data lane
436 + Support for up to 6 GBaud operation
437 + - High-speed peripheral interfaces:
438 + - One PCI Express Gen2 controller, supporting x1 operation
439 + - One serial ATA (SATA Gen 3.0) controller
440 + - One USB 3.0/2.0 controller with integrated PHY
441 + - One USB 2.0 controller with ULPI interface. .
442 + - Additional peripheral interfaces:
443 + - One quad serial peripheral interface (QuadSPI) controller
444 + - One serial peripheral interface (SPI) controller
445 + - Two enhanced secure digital host controllers
446 + - Two I2C controllers
447 + - One 16550 compliant DUART (two UART interfaces)
448 + - Two general purpose IOs (GPIO)
449 + - Two FlexTimers
450 + - Five synchronous audio interfaces (SAI)
451 + - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
452 + - Single-source clocking solution enabling generation of core, platform,
453 + DDR, SerDes, and USB clocks from a single external crystal and internal
454 + crystaloscillator
455 + - Thermal monitor unit (TMU) with +/- 3C accuracy
456 + - Two WatchDog timers
457 + - ARM generic timer
458 + - QorIQ platform's trust architecture 2.1
459 +
460 + LS1012AQDS board Overview
461 + -----------------------
462 + - SERDES Connections, 4 lanes supporting:
463 + - PCI Express - 3.0
464 + - SGMII, SGMII 2.5
465 + - SATA 3.0
466 + - DDR Controller
467 + - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
468 + - QSPI Controller
469 + - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
470 + signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
471 + emulator
472 + - USB 3.0
473 + - One USB 3.0 controller with integrated PHY
474 + - One high-speed USB 3.0 port
475 + - USB 2.0
476 + - One USB 2.0 controller with ULPI interface
477 + - Two enhanced secure digital host controllers:
478 + - SDHC1 controller can be connected to onboard SDHC connector
479 + - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
480 + - 2 I2C controllers
481 + - One SATA onboard connectors
482 + - UART
483 + - 5 SAI
484 + - One SAI port with audio codec SGTL5000:
485 + • Provides MIC bias
486 + • Provides headphone and line output
487 + - One SAI port terminated at 2x6 header
488 + - Three SAI Tx/Rx ports terminated at 2x3 headers
489 + - ARM JTAG support
490 +
491 +Booting Options
492 +---------------
493 +a) QSPI Flash Emu Boot
494 +b) QSPI Flash 1
495 +c) QSPI Flash 2
496 +
497 +QSPI flash map
498 +--------------
499 +Images | Size |QSPI Flash Address
500 +------------------------------------------
501 +RCW + PBI | 1MB | 0x4000_0000
502 +U-boot | 1MB | 0x4010_0000
503 +U-boot Env | 1MB | 0x4020_0000
504 +PPA FIT image | 2MB | 0x4050_0000
505 +Linux ITB | ~53MB | 0x40A0_0000
506 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
507 new file mode 100644
508 index 0000000..ffcd0d8
509 --- /dev/null
510 +++ b/board/freescale/ls1012aqds/ls1012aqds.c
511 @@ -0,0 +1,199 @@
512 +/*
513 + * Copyright 2016 Freescale Semiconductor, Inc.
514 + *
515 + * SPDX-License-Identifier: GPL-2.0+
516 + */
517 +
518 +#include <common.h>
519 +#include <i2c.h>
520 +#include <fdt_support.h>
521 +#include <asm/io.h>
522 +#include <asm/arch/clock.h>
523 +#include <asm/arch/fsl_serdes.h>
524 +#include <asm/arch/fdt.h>
525 +#include <asm/arch/soc.h>
526 +#include <ahci.h>
527 +#include <hwconfig.h>
528 +#include <mmc.h>
529 +#include <scsi.h>
530 +#include <fm_eth.h>
531 +#include <fsl_csu.h>
532 +#include <fsl_esdhc.h>
533 +#include <fsl_mmdc.h>
534 +#include <spl.h>
535 +#include <netdev.h>
536 +
537 +#include "../common/qixis.h"
538 +#include "ls1012aqds_qixis.h"
539 +
540 +DECLARE_GLOBAL_DATA_PTR;
541 +
542 +int checkboard(void)
543 +{
544 + puts("Board: LS1012AQDS\n");
545 +
546 + return 0;
547 +}
548 +
549 +void mmdc_init(void)
550 +{
551 + struct mmdc_p_regs *mmdc =
552 + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
553 +
554 + /* Set MMDC_MDSCR[CON_REQ] */
555 + out_be32(&mmdc->mdscr, 0x00008000);
556 +
557 + /* configure timing parms */
558 + out_be32(&mmdc->mdotc, 0x12554000);
559 + out_be32(&mmdc->mdcfg0, 0xbabf7954);
560 + out_be32(&mmdc->mdcfg1, 0xff328f64);
561 + out_be32(&mmdc->mdcfg2, 0x01ff00db);
562 +
563 + /* other parms */
564 + out_be32(&mmdc->mdmisc, 0x00000680);
565 + out_be32(&mmdc->mpmur0, 0x00000800);
566 + out_be32(&mmdc->mdrwd, 0x00002000);
567 + out_be32(&mmdc->mpodtctrl, 0x0000022a);
568 +
569 + /* out of reset delays */
570 + out_be32(&mmdc->mdor, 0x00bf1023);
571 +
572 + /* physical parms */
573 + out_be32(&mmdc->mdctl, 0x05180000);
574 + out_be32(&mmdc->mdasp, 0x0000007f);
575 +
576 + /* Enable MMDC */
577 + out_be32(&mmdc->mdctl, 0x85180000);
578 +
579 + /* dram init sequence: update MRs */
580 + out_be32(&mmdc->mdscr, 0x00088032);
581 + out_be32(&mmdc->mdscr, 0x00008033);
582 + out_be32(&mmdc->mdscr, 0x00048031);
583 + out_be32(&mmdc->mdscr, 0x19308030);
584 +
585 + /* dram init sequence: ZQCL */
586 + out_be32(&mmdc->mdscr, 0x04008040);
587 + out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
588 +
589 + mdelay(100);
590 +
591 + /* Calibrations now: wr lvl */
592 + out_be32(&mmdc->mdscr, 0x00848031);
593 + out_be32(&mmdc->mdscr, 0x00008200);
594 + out_be32(&mmdc->mpwlgcr, 0x00000001);
595 +
596 + mdelay(100);
597 +
598 + out_be32(&mmdc->mdscr, 0x00048031);
599 + out_be32(&mmdc->mdscr, 0x00008000);
600 +
601 + /* manual_refresh */
602 + out_be32(&mmdc->mdscr, 0x00008020);
603 +
604 + mdelay(100);
605 +
606 + /* Calibrations now: Read DQS gating calibration */
607 + out_be32(&mmdc->mdscr, 0x04008050);
608 + out_be32(&mmdc->mdscr, 0x00048033);
609 + out_be32(&mmdc->mppdcmpr2, 0x00000001);
610 + out_be32(&mmdc->mprddlctl, 0x40404040);
611 + out_be32(&mmdc->mpdgctrl0, 0x10000000);
612 +
613 + mdelay(100);
614 +
615 + out_be32(&mmdc->mdscr, 0x00008033);
616 +
617 + /* manual_refresh */
618 + out_be32(&mmdc->mdscr, 0x00008020);
619 +
620 + mdelay(100);
621 +
622 + /* Calibrations now: Read calibration */
623 + out_be32(&mmdc->mdscr, 0x04008050);
624 + out_be32(&mmdc->mdscr, 0x00048033);
625 + out_be32(&mmdc->mppdcmpr2, 0x00000001);
626 + out_be32(&mmdc->mprddlhwctl, 0x00000010);
627 +
628 + mdelay(400);
629 +
630 + out_be32(&mmdc->mdscr, 0x00008033);
631 +
632 + /* manual_refresh */
633 + out_be32(&mmdc->mdscr, 0x00008020);
634 +
635 + mdelay(100);
636 +
637 + /* PD, SR */
638 + out_be32(&mmdc->mdpdc, 0x00030035);
639 + out_be32(&mmdc->mapsr, 0x00001067);
640 +
641 + /* refresh scheme */
642 + out_be32(&mmdc->mdref, 0x103e8000);
643 +
644 + mdelay(400);
645 +
646 + /* disable CON_REQ */
647 + out_be32(&mmdc->mdscr, 0x0);
648 +
649 + mdelay(50);
650 +}
651 +
652 +int dram_init(void)
653 +{
654 + mmdc_init();
655 +
656 + gd->ram_size = 0x40000000;
657 +
658 + return 0;
659 +}
660 +
661 +int board_early_init_f(void)
662 +{
663 + fsl_lsch2_early_init_f();
664 +
665 + return 0;
666 +}
667 +
668 +int board_init(void)
669 +{
670 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
671 + CONFIG_SYS_CCI400_ADDR;
672 +
673 + /* Set CCI-400 control override register to enable barrier
674 + * transaction */
675 + out_le32(&cci->ctrl_ord,
676 + CCI400_CTRLORD_EN_BARRIER);
677 +
678 +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
679 + enable_layerscape_ns_access();
680 +#endif
681 +
682 +#ifdef CONFIG_ENV_IS_NOWHERE
683 + gd->env_addr = (ulong)&default_environment[0];
684 +#endif
685 + return 0;
686 +}
687 +
688 +int board_eth_init(bd_t *bis)
689 +{
690 + return pci_eth_init(bis);
691 +}
692 +
693 +#ifdef CONFIG_OF_BOARD_SETUP
694 +int ft_board_setup(void *blob, bd_t *bd)
695 +{
696 + u64 base[CONFIG_NR_DRAM_BANKS];
697 + u64 size[CONFIG_NR_DRAM_BANKS];
698 +
699 + /* fixup DT for the two DDR banks */
700 + base[0] = gd->bd->bi_dram[0].start;
701 + size[0] = gd->bd->bi_dram[0].size;
702 + base[1] = gd->bd->bi_dram[1].start;
703 + size[1] = gd->bd->bi_dram[1].size;
704 +
705 + fdt_fixup_memory_banks(blob, base, size, 2);
706 + ft_cpu_setup(blob, bd);
707 +
708 + return 0;
709 +}
710 +#endif
711 diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
712 new file mode 100644
713 index 0000000..584f604
714 --- /dev/null
715 +++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
716 @@ -0,0 +1,35 @@
717 +/*
718 + * Copyright 2016 Freescale Semiconductor, Inc.
719 + *
720 + * SPDX-License-Identifier: GPL-2.0+
721 + */
722 +
723 +#ifndef __LS1043AQDS_QIXIS_H__
724 +#define __LS1043AQDS_QIXIS_H__
725 +
726 +/* Definitions of QIXIS Registers for LS1043AQDS */
727 +
728 +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
729 +#define BRDCFG4_EMISEL_MASK 0xe0
730 +#define BRDCFG4_EMISEL_SHIFT 5
731 +
732 +/* SYSCLK */
733 +#define QIXIS_SYSCLK_66 0x0
734 +#define QIXIS_SYSCLK_83 0x1
735 +#define QIXIS_SYSCLK_100 0x2
736 +#define QIXIS_SYSCLK_125 0x3
737 +#define QIXIS_SYSCLK_133 0x4
738 +
739 +/* DDRCLK */
740 +#define QIXIS_DDRCLK_66 0x0
741 +#define QIXIS_DDRCLK_100 0x1
742 +#define QIXIS_DDRCLK_125 0x2
743 +#define QIXIS_DDRCLK_133 0x3
744 +
745 +/* BRDCFG2 - SD clock*/
746 +#define QIXIS_SDCLK1_100 0x0
747 +#define QIXIS_SDCLK1_125 0x1
748 +#define QIXIS_SDCLK1_165 0x2
749 +#define QIXIS_SDCLK1_100_SP 0x3
750 +
751 +#endif
752 diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
753 new file mode 100644
754 index 0000000..ef2c0ad
755 --- /dev/null
756 +++ b/configs/ls1012aqds_qspi_defconfig
757 @@ -0,0 +1,10 @@
758 +CONFIG_ARM=y
759 +CONFIG_TARGET_LS1012AQDS=y
760 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
761 +# CONFIG_CMD_IMLS is not set
762 +CONFIG_SYS_NS16550=y
763 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
764 +CONFIG_OF_CONTROL=y
765 +CONFIG_DM=y
766 +CONFIG_SPI_FLASH=y
767 +CONFIG_DM_SPI=y
768 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
769 new file mode 100644
770 index 0000000..9ed04f9
771 --- /dev/null
772 +++ b/include/configs/ls1012a_common.h
773 @@ -0,0 +1,239 @@
774 +/*
775 + * Copyright (C) 2015 Freescale Semiconductor
776 + *
777 + * SPDX-License-Identifier: GPL-2.0+
778 + */
779 +
780 +#ifndef __LS1012A_COMMON_H
781 +#define __LS1012A_COMMON_H
782 +
783 +#define CONFIG_FSL_LAYERSCAPE
784 +#define CONFIG_FSL_LSCH2
785 +#define CONFIG_LS1012A
786 +#define CONFIG_GICV2
787 +
788 +#define CONFIG_SYS_HAS_SERDES
789 +
790 +#include <asm/arch/config.h>
791 +#define CONFIG_SYS_NO_FLASH
792 +
793 +#define CONFIG_SUPPORT_RAW_INITRD
794 +
795 +#define CONFIG_DISPLAY_BOARDINFO_LATE
796 +
797 +#define CONFIG_SYS_TEXT_BASE 0x40100000
798 +
799 +#define CONFIG_SYS_FSL_CLK
800 +#define CONFIG_SYS_CLK_FREQ 100000000
801 +#define CONFIG_DDR_CLK_FREQ 125000000
802 +
803 +#define CONFIG_SKIP_LOWLEVEL_INIT
804 +#define CONFIG_BOARD_EARLY_INIT_F 1
805 +
806 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
807 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
808 +
809 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
810 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
811 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
812 +
813 +/* Generic Timer Definitions */
814 +#define COUNTER_FREQUENCY 25000000 /* 12MHz */
815 +
816 +/* CSU */
817 +#define CONFIG_LAYERSCAPE_NS_ACCESS
818 +
819 +/* Size of malloc() pool */
820 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
821 +
822 +/*SPI device */
823 +#ifdef CONFIG_QSPI_BOOT
824 +#define CONFIG_SYS_QE_FW_IN_SPIFLASH
825 +#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
826 +#define CONFIG_ENV_SPI_BUS 0
827 +#define CONFIG_ENV_SPI_CS 0
828 +#define CONFIG_ENV_SPI_MAX_HZ 1000000
829 +#define CONFIG_ENV_SPI_MODE 0x03
830 +#define CONFIG_CMD_SF
831 +#define CONFIG_SPI_FLASH_SPANSION
832 +#define CONFIG_SPI_FLASH_ATMEL
833 +#define CONFIG_FSL_SPI_INTERFACE
834 +#define CONFIG_SF_DATAFLASH
835 +
836 +#define CONFIG_FSL_QSPI
837 +#define QSPI0_AMBA_BASE 0x40000000
838 +#define CONFIG_SPI_FLASH_SPANSION
839 +#define CONFIG_DM_SPI_FLASH
840 +#define CONFIG_SPI_FLASH_BAR
841 +
842 +#define FSL_QSPI_FLASH_SIZE (1 << 24)
843 +#define FSL_QSPI_FLASH_NUM 2
844 +
845 +/*
846 + * Environment
847 + */
848 +#define CONFIG_ENV_OVERWRITE
849 +
850 +#define CONFIG_ENV_IS_IN_SPI_FLASH
851 +#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
852 +#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
853 +#define CONFIG_ENV_SECT_SIZE 0x40000
854 +#endif
855 +
856 +/* I2C */
857 +#if !defined(CONFIG_EMU)
858 +#define CONFIG_CMD_I2C
859 +#define CONFIG_SYS_I2C
860 +#define CONFIG_SYS_I2C_MXC
861 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
862 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
863 +#endif /* CONFIG_EMU */
864 +
865 +/* MMC */
866 +#if !defined(CONFIG_EMU)
867 +#define CONFIG_MMC
868 +#ifdef CONFIG_MMC
869 +#define CONFIG_CMD_MMC
870 +#define CONFIG_FSL_ESDHC
871 +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
872 +#define CONFIG_GENERIC_MMC
873 +#define CONFIG_CMD_FAT
874 +#define CONFIG_DOS_PARTITION
875 +#endif
876 +#endif /* CONFIG_EMU */
877 +
878 +/* SATA */
879 +#if !defined(CONFIG_EMU)
880 +#define CONFIG_LIBATA
881 +#define CONFIG_SCSI_AHCI
882 +#define CONFIG_SCSI_AHCI_PLAT
883 +#define CONFIG_CMD_SCSI
884 +#define CONFIG_CMD_FAT
885 +#define CONFIG_CMD_EXT2
886 +#define CONFIG_DOS_PARTITION
887 +#define CONFIG_BOARD_LATE_INIT
888 +
889 +#define CONFIG_SYS_SATA AHCI_BASE_ADDR
890 +
891 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
892 +#define CONFIG_SYS_SCSI_MAX_LUN 1
893 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
894 + CONFIG_SYS_SCSI_MAX_LUN)
895 +
896 +#define CONFIG_PCI /* Enable PCI/PCIE */
897 +#define CONFIG_PCIE1 /* PCIE controller 1 */
898 +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
899 +#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
900 +
901 +#define CONFIG_SYS_PCI_64BIT
902 +
903 +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
904 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
905 +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
906 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
907 +
908 +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
909 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
910 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
911 +
912 +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
913 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
914 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
915 +
916 +#define CONFIG_NET_MULTI
917 +#define CONFIG_PCI_PNP
918 +#define CONFIG_E1000
919 +#define CONFIG_PCI_SCAN_SHOW
920 +#define CONFIG_CMD_PCI
921 +#endif
922 +
923 +#define CONFIG_CONS_INDEX 1
924 +#define CONFIG_SYS_NS16550_SERIAL
925 +#define CONFIG_SYS_NS16550_REG_SIZE 1
926 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
927 +
928 +#ifdef CONFIG_EMU
929 +#define CONFIG_BAUDRATE 3000
930 +#else
931 +#define CONFIG_BAUDRATE 115200
932 +#endif
933 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
934 +
935 +/* Command line configuration */
936 +#define CONFIG_CMD_CACHE
937 +#define CONFIG_CMD_DHCP
938 +#define CONFIG_CMD_ENV
939 +#define CONFIG_CMD_GREPENV
940 +#define CONFIG_CMD_MII
941 +#define CONFIG_CMD_PING
942 +#undef CONFIG_CMD_IMLS
943 +
944 +
945 +#define CONFIG_ARCH_EARLY_INIT_R
946 +
947 +#define CONFIG_SYS_HZ 1000
948 +
949 +#define CONFIG_HWCONFIG
950 +#define HWCONFIG_BUFFER_SIZE 128
951 +
952 +#define CONFIG_DISPLAY_CPUINFO
953 +
954 +/* Initial environment variables */
955 +#define CONFIG_EXTRA_ENV_SETTINGS \
956 + "initrd_high=0xffffffff\0" \
957 + "verify=no\0" \
958 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
959 + "loadaddr=0x80100000\0" \
960 + "kernel_addr=0x100000\0" \
961 + "ramdisk_addr=0x800000\0" \
962 + "ramdisk_size=0x2000000\0" \
963 + "fdt_high=0xffffffffffffffff\0" \
964 + "initrd_high=0xffffffffffffffff\0" \
965 + "kernel_start=0xa00000\0" \
966 + "kernel_load=0xa0000000\0" \
967 + "kernel_size=0x2800000\0" \
968 + "console=ttyAMA0,38400n8\0"
969 +
970 +#ifdef CONFIG_EMU
971 +#define CONFIG_BOOTARGS "console=ttyS2,115200 root=/dev/ram0 " \
972 + "earlycon=uart8250,mmio,0x21d0500,115200n8"
973 +/* Kernel image should be pre-loaded to address kernel_load */
974 +#define CONFIG_BOOTCOMMAND "bootm $kernel_load"
975 +#else
976 +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
977 + "earlycon=uart8250,mmio,0x21c0500"
978 +#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
979 + "$kernel_start $kernel_size && "\
980 + "bootm $kernel_load"
981 +#endif
982 +#define CONFIG_BOOTDELAY 10
983 +
984 +/* Monitor Command Prompt */
985 +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
986 +#define CONFIG_SYS_PROMPT "=> "
987 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
988 + sizeof(CONFIG_SYS_PROMPT) + 16)
989 +#define CONFIG_SYS_HUSH_PARSER
990 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
991 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
992 +#define CONFIG_SYS_LONGHELP
993 +#define CONFIG_CMDLINE_EDITING 1
994 +#define CONFIG_AUTO_COMPLETE
995 +#define CONFIG_SYS_MAXARGS 64 /* max command args */
996 +
997 +#define CONFIG_PANIC_HANG
998 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
999 +
1000 +/* Flat Device Tree Definitions */
1001 +#define CONFIG_OF_LIBFDT
1002 +#define CONFIG_OF_BOARD_SETUP
1003 +
1004 +/* new uImage format support */
1005 +#define CONFIG_FIT
1006 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
1007 +#define CONFIG_CMD_BOOTZ
1008 +#define CONFIG_CMDLINE_TAG
1009 +
1010 +#include <asm/fsl_secure_boot.h>
1011 +
1012 +#endif /* __LS1012A_COMMON_H */
1013 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
1014 new file mode 100644
1015 index 0000000..6346d3e
1016 --- /dev/null
1017 +++ b/include/configs/ls1012aqds.h
1018 @@ -0,0 +1,133 @@
1019 +/*
1020 + * Copyright 2016 Freescale Semiconductor, Inc.
1021 + *
1022 + * SPDX-License-Identifier: GPL-2.0+
1023 + */
1024 +
1025 +#ifndef __LS1012AQDS_H__
1026 +#define __LS1012AQDS_H__
1027 +
1028 +#include "ls1012a_common.h"
1029 +
1030 +
1031 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
1032 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1
1033 +#define CONFIG_NR_DRAM_BANKS 2
1034 +
1035 +#ifdef CONFIG_SYS_DPAA_FMAN
1036 +#define CONFIG_FMAN_ENET
1037 +#define CONFIG_PHYLIB
1038 +#define CONFIG_PHY_VITESSE
1039 +#define CONFIG_PHY_REALTEK
1040 +#define RGMII_PHY1_ADDR 0x1
1041 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
1042 +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
1043 +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
1044 +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
1045 +#endif
1046 +
1047 +#define CONFIG_QIXIS_I2C_ACCESS
1048 +
1049 +/*
1050 + * I2C bus multiplexer
1051 + */
1052 +#define I2C_MUX_PCA_ADDR_PRI 0x77
1053 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
1054 +#define I2C_RETIMER_ADDR 0x18
1055 +#define I2C_MUX_CH_DEFAULT 0x8
1056 +#define I2C_MUX_CH_CH7301 0xC
1057 +#define I2C_MUX_CH5 0xD
1058 +#define I2C_MUX_CH7 0xF
1059 +
1060 +#define I2C_MUX_CH_VOL_MONITOR 0xa
1061 +
1062 +/*
1063 +* RTC configuration
1064 +*/
1065 +#define RTC
1066 +#define CONFIG_RTC_PCF8563 1
1067 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
1068 +#define CONFIG_CMD_DATE
1069 +
1070 +/* EEPROM */
1071 +#define CONFIG_ID_EEPROM
1072 +#define CONFIG_CMD_EEPROM
1073 +#define CONFIG_SYS_I2C_EEPROM_NXID
1074 +#define CONFIG_SYS_EEPROM_BUS_NUM 0
1075 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
1076 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
1077 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
1078 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
1079 +
1080 +
1081 +/* Voltage monitor on channel 2*/
1082 +#define I2C_VOL_MONITOR_ADDR 0x40
1083 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
1084 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
1085 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
1086 +
1087 +/* DSPI */
1088 +#define CONFIG_FSL_DSPI
1089 +#define CONFIG_FSL_DSPI1
1090 +#define CONFIG_DEFAULT_SPI_BUS 1
1091 +
1092 +#define CONFIG_CMD_SPI
1093 +#define MMAP_DSPI DSPI1_BASE_ADDR
1094 +
1095 +#define CONFIG_SYS_DSPI_CTAR0 1
1096 +
1097 +#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
1098 + DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
1099 + DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
1100 + DSPI_CTAR_DT(0))
1101 +#define CONFIG_SPI_FLASH_SST /* cs1 */
1102 +
1103 +#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
1104 + DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
1105 + DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
1106 + DSPI_CTAR_DT(0))
1107 +#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
1108 +
1109 +#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
1110 + DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
1111 + DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
1112 + DSPI_CTAR_DT(0))
1113 +#define CONFIG_SPI_FLASH_EON /* cs3 */
1114 +
1115 +#define CONFIG_SF_DEFAULT_SPEED 10000000
1116 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
1117 +#define CONFIG_SF_DEFAULT_BUS 1
1118 +#define CONFIG_SF_DEFAULT_CS 0
1119 +
1120 +/*
1121 +* USB
1122 +*/
1123 +/* EHCI Support - disbaled by default */
1124 +/*#define CONFIG_HAS_FSL_DR_USB*/
1125 +
1126 +#ifdef CONFIG_HAS_FSL_DR_USB
1127 +#define CONFIG_USB_EHCI
1128 +#define CONFIG_USB_EHCI_FSL
1129 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
1130 +#endif
1131 +
1132 +/*XHCI Support - enabled by default*/
1133 +#define CONFIG_HAS_FSL_XHCI_USB
1134 +
1135 +#ifdef CONFIG_HAS_FSL_XHCI_USB
1136 +#define CONFIG_USB_XHCI
1137 +#define CONFIG_USB_XHCI_FSL
1138 +#define CONFIG_USB_XHCI_DWC3
1139 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
1140 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
1141 +#define CONFIG_CMD_USB
1142 +#define CONFIG_USB_STORAGE
1143 +#define CONFIG_CMD_EXT2
1144 +#endif
1145 +
1146 +#define CONFIG_CMD_MEMINFO
1147 +#define CONFIG_CMD_MEMTEST
1148 +#define CONFIG_SYS_MEMTEST_START 0x80000000
1149 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
1150 +
1151 +#endif /* __LS1012AQDS_H__ */
1152 diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
1153 index 3df822e..d47e625 100644
1154 --- a/include/fsl_mmdc.h
1155 +++ b/include/fsl_mmdc.h
1156 @@ -25,29 +25,70 @@ struct mmdc_p_regs {
1157 u32 mdcfg3lp;
1158 u32 mdmr4;
1159 u32 mdasp;
1160 - u32 res3[239];
1161 + u32 res2[239];
1162 u32 maarcr;
1163 u32 mapsr;
1164 - u32 res4[254];
1165 + u32 maexidr0;
1166 + u32 maexidr1;
1167 + u32 madpcr0;
1168 + u32 madpcr1;
1169 + u32 madpsr0;
1170 + u32 madpsr1;
1171 + u32 madpsr2;
1172 + u32 madpsr3;
1173 + u32 madpsr4;
1174 + u32 madpsr5;
1175 + u32 masbs0;
1176 + u32 masbs1;
1177 + u32 res3[2];
1178 + u32 magenp;
1179 + u32 res4[239];
1180 u32 mpzqhwctrl;
1181 - u32 res5[2];
1182 + u32 mpzqswctrl;
1183 + u32 mpwlgcr;
1184 u32 mpwldectrl0;
1185 u32 mpwldectrl1;
1186 - u32 res6;
1187 + u32 mpwldlst;
1188 u32 mpodtctrl;
1189 u32 mprddqby0dl;
1190 u32 mprddqby1dl;
1191 u32 mprddqby2dl;
1192 u32 mprddqby3dl;
1193 - u32 res7[4];
1194 + u32 res5[4];
1195 u32 mpdgctrl0;
1196 u32 mpdgctrl1;
1197 - u32 res8;
1198 + u32 mpdgdlst0;
1199 u32 mprddlctl;
1200 - u32 res9;
1201 + u32 mprddlst;
1202 u32 mpwrdlctl;
1203 - u32 res10[25];
1204 + u32 mpwrdlst;
1205 + u32 mpsdctrl;
1206 + u32 mpzqlp2ctl;
1207 + u32 mprddlhwctl;
1208 + u32 mpwrdlhwctl;
1209 + u32 mprddlhwst0;
1210 + u32 mprddlhwst1;
1211 + u32 mpwrdlhwst0;
1212 + u32 mpwrdlhwst1;
1213 + u32 mpwlhwerr;
1214 + u32 mpdghwst0;
1215 + u32 mpdghwst1;
1216 + u32 mpdghwst2;
1217 + u32 mpdghwst3;
1218 + u32 mppdcmpr1;
1219 + u32 mppdcmpr2;
1220 + u32 mpswdar0;
1221 + u32 mpswdrdr0;
1222 + u32 mpswdrdr1;
1223 + u32 mpswdrdr2;
1224 + u32 mpswdrdr3;
1225 + u32 mpswdrdr4;
1226 + u32 mpswdrdr5;
1227 + u32 mpswdrdr6;
1228 + u32 mpswdrdr7;
1229 u32 mpmur0;
1230 + u32 mpwrcadl;
1231 + u32 mpdccr;
1232 };
1233
1234 #endif /* FSL_MMDC_H */
1235 --
1236 1.7.9.5
1237
OpenWrt Source Repository