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uboot-lantiq: Add BT Home Hub 5A support
[openwrt/openwrt.git] / package / boot / uboot-lantiq / patches / 0116-MIPS-add-board-support-for-BT-Home-Hub-5A.patch
1 --- /dev/null
2 +++ b/board/bt/bthomehubv5a/Makefile
3 @@ -0,0 +1,27 @@
4 +#
5 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
6 +#
7 +# SPDX-License-Identifier: GPL-2.0+
8 +#
9 +
10 +include $(TOPDIR)/config.mk
11 +
12 +LIB = $(obj)lib$(BOARD).o
13 +
14 +COBJS = $(BOARD).o
15 +
16 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
17 +OBJS := $(addprefix $(obj),$(COBJS))
18 +SOBJS := $(addprefix $(obj),$(SOBJS))
19 +
20 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
21 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
22 +
23 +#########################################################################
24 +
25 +# defines $(obj).depend target
26 +include $(SRCTREE)/rules.mk
27 +
28 +sinclude $(obj).depend
29 +
30 +#########################################################################
31 --- /dev/null
32 +++ b/board/bt/bthomehubv5a/bthomehubv5a.c
33 @@ -0,0 +1,125 @@
34 +/*
35 + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
36 + * Based on p2812hnufx.c: (C) 2013 Luka Perkov <luka@openwrt.org>
37 + *
38 + * SPDX-License-Identifier: GPL-2.0+
39 + */
40 +
41 +#include <common.h>
42 +#include <asm/gpio.h>
43 +#include <asm/lantiq/eth.h>
44 +#include <asm/lantiq/chipid.h>
45 +#include <asm/lantiq/cpu.h>
46 +#include <asm/arch/gphy.h>
47 +
48 +#if defined(CONFIG_SPL_BUILD)
49 +#define do_gpio_init 1
50 +#define do_pll_init 1
51 +#define do_dcdc_init 0
52 +#elif defined(CONFIG_SYS_BOOT_RAM)
53 +#define do_gpio_init 1
54 +#define do_pll_init 0
55 +#define do_dcdc_init 1
56 +#else
57 +#define do_gpio_init 0
58 +#define do_pll_init 0
59 +#define do_dcdc_init 1
60 +#endif
61 +
62 +#define GPIO_POWER_GREEN 14
63 +#define GPIO_POWER_RED 12
64 +
65 +static void gpio_init(void)
66 +{
67 + /* EBU.FL_CS1 as output for NAND CE */
68 + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
69 + /* EBU.FL_A23 as output for NAND CLE */
70 + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
71 + /* EBU.FL_A24 as output for NAND ALE */
72 + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
73 + /* GPIO 3.0 as input for NAND Ready Busy */
74 + gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
75 + /* GPIO 3.1 as output for NAND Read */
76 + gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
77 +
78 + /* Turn on the green power LED */
79 + gpio_direction_output(GPIO_POWER_GREEN, 0);
80 +
81 + /* Turn off the red power LED */
82 + gpio_direction_output(GPIO_POWER_RED, 1);
83 +}
84 +
85 +int board_early_init_f(void)
86 +{
87 + if (do_gpio_init)
88 + gpio_init();
89 +
90 + if (do_pll_init)
91 + ltq_pll_init();
92 +
93 + if (do_dcdc_init)
94 + ltq_dcdc_init(0x7F);
95 +
96 + return 0;
97 +}
98 +
99 +int checkboard(void)
100 +{
101 + puts("Board: " CONFIG_BOARD_NAME "\n");
102 + ltq_chip_print_info();
103 +
104 + return 0;
105 +}
106 +
107 +void show_boot_progress(int arg)
108 +{
109 + if (!do_gpio_init)
110 + return 0;
111 +
112 + if (arg >= 0) {
113 + /* Success - turn off the red power LED and turn on the green power LED */
114 + gpio_set_value(GPIO_POWER_RED, 1);
115 + gpio_set_value(GPIO_POWER_GREEN, 0);
116 + } else {
117 + /* Failure - turn off green power LED and turn on red power LED */
118 + gpio_set_value(GPIO_POWER_GREEN, 1);
119 + gpio_set_value(GPIO_POWER_RED, 0);
120 + }
121 +
122 + return 0;
123 +}
124 +
125 +static const struct ltq_eth_port_config eth_port_config[] = {
126 + /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 3 */
127 + { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
128 + /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 4 */
129 + { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
130 + /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
131 + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
132 + /* GMAC3: unused */
133 + { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
134 + /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 1 */
135 + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
136 + /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
137 + { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
138 +};
139 +
140 +static const struct ltq_eth_board_config eth_board_config = {
141 + .ports = eth_port_config,
142 + .num_ports = ARRAY_SIZE(eth_port_config),
143 +};
144 +
145 +int board_eth_init(bd_t * bis)
146 +{
147 + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
148 + const ulong fw_addr = 0x80FE0000;
149 +
150 + ltq_gphy_phy11g_a2x_load(fw_addr);
151 +
152 + ltq_cgu_gphy_clk_src(clk);
153 +
154 + ltq_rcu_gphy_boot(0, fw_addr);
155 + ltq_rcu_gphy_boot(1, fw_addr);
156 +
157 + return ltq_eth_initialize(&eth_board_config);
158 +}
159 --- /dev/null
160 +++ b/board/bt/bthomehubv5a/config.mk
161 @@ -0,0 +1,7 @@
162 +#
163 +# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
164 +#
165 +# SPDX-License-Identifier: GPL-2.0+
166 +#
167 +
168 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
169 --- /dev/null
170 +++ b/board/bt/bthomehubv5a/ddr_settings.h
171 @@ -0,0 +1,70 @@
172 +/*
173 + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
174 + *
175 + * The values have been taken from the HH5A GPL source.
176 + *
177 + * SPDX-License-Identifier: GPL-2.0+
178 + */
179 +
180 +#define MC_CCR00_VALUE 0x101
181 +#define MC_CCR01_VALUE 0x1000101
182 +#define MC_CCR02_VALUE 0x1010000
183 +#define MC_CCR03_VALUE 0x101
184 +#define MC_CCR04_VALUE 0x1000000
185 +#define MC_CCR05_VALUE 0x1000101
186 +#define MC_CCR06_VALUE 0x1000100
187 +#define MC_CCR07_VALUE 0x1010000
188 +#define MC_CCR08_VALUE 0x1000101
189 +#define MC_CCR09_VALUE 0x0
190 +#define MC_CCR10_VALUE 0x2000100
191 +#define MC_CCR11_VALUE 0x2000401
192 +#define MC_CCR12_VALUE 0x30000
193 +#define MC_CCR13_VALUE 0x202
194 +#define MC_CCR14_VALUE 0x7080A0F
195 +#define MC_CCR15_VALUE 0x2040F
196 +#define MC_CCR16_VALUE 0x40000
197 +#define MC_CCR17_VALUE 0x70102
198 +#define MC_CCR18_VALUE 0x4020002
199 +#define MC_CCR19_VALUE 0x30302
200 +#define MC_CCR20_VALUE 0x8000700
201 +#define MC_CCR21_VALUE 0x40F020A
202 +#define MC_CCR22_VALUE 0x0
203 +#define MC_CCR23_VALUE 0xC020000
204 +#define MC_CCR24_VALUE 0x4401B04
205 +#define MC_CCR25_VALUE 0x0
206 +#define MC_CCR26_VALUE 0x0
207 +#define MC_CCR27_VALUE 0x6420000
208 +#define MC_CCR28_VALUE 0x0
209 +#define MC_CCR29_VALUE 0x0
210 +#define MC_CCR30_VALUE 0x798
211 +#define MC_CCR31_VALUE 0x0
212 +#define MC_CCR32_VALUE 0x0
213 +#define MC_CCR33_VALUE 0x650000
214 +#define MC_CCR34_VALUE 0x200C8
215 +#define MC_CCR35_VALUE 0x1D445D
216 +#define MC_CCR36_VALUE 0xC8
217 +#define MC_CCR37_VALUE 0xC351
218 +#define MC_CCR38_VALUE 0x0
219 +#define MC_CCR39_VALUE 0x141F04
220 +#define MC_CCR40_VALUE 0x142704
221 +#define MC_CCR41_VALUE 0x141b42
222 +#define MC_CCR42_VALUE 0x141b42
223 +#define MC_CCR43_VALUE 0x566504
224 +#define MC_CCR44_VALUE 0x566504
225 +#define MC_CCR45_VALUE 0x565F17
226 +#define MC_CCR46_VALUE 0x565F17
227 +#define MC_CCR47_VALUE 0x0
228 +#define MC_CCR48_VALUE 0x0
229 +#define MC_CCR49_VALUE 0x0
230 +#define MC_CCR50_VALUE 0x0
231 +#define MC_CCR51_VALUE 0x0
232 +#define MC_CCR52_VALUE 0x133
233 +#define MC_CCR53_VALUE 0xF3014B27
234 +#define MC_CCR54_VALUE 0xF3014B27
235 +#define MC_CCR55_VALUE 0xF3014B27
236 +#define MC_CCR56_VALUE 0xF3014B27
237 +#define MC_CCR57_VALUE 0x7800301
238 +#define MC_CCR58_VALUE 0x7800301
239 +#define MC_CCR59_VALUE 0x7800301
240 +#define MC_CCR60_VALUE 0x7800301
241 +#define MC_CCR61_VALUE 0x4
242 --- a/boards.cfg
243 +++ b/boards.cfg
244 @@ -546,6 +546,8 @@ Active mips mips32 vrx20
245 Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
246 Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
247 Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
248 +Active mips mips32 vrx200 bt bthomehubv5a bthomehubv5a_nandspl bthomehubv5a:SYS_BOOT_NANDSPL Martin Blumenstingl <martin.blumenstingl@googlemail.com>
249 +Active mips mips32 vrx200 bt bthomehubv5a bthomehubv5a_ram bthomehubv5a:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com>
250 Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
251 Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
252 Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
253 --- /dev/null
254 +++ b/include/configs/bthomehubv5a.h
255 @@ -0,0 +1,89 @@
256 +/*
257 + * Copyright (C) 2016 Mathias Kresin <openwrt@kresin.me>
258 + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
259 + * Based on p2812hnufx.h: (C) 2013 Luka Perkov <luka@openwrt.org>
260 + *
261 + * SPDX-License-Identifier: GPL-2.0+
262 + */
263 +
264 +#ifndef __CONFIG_H
265 +#define __CONFIG_H
266 +
267 +#define CONFIG_MACH_TYPE "BTHOMEHUBV5A"
268 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
269 +#define CONFIG_BOARD_NAME "BT Home Hub 5A"
270 +
271 +/* Configure SoC */
272 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
273 +
274 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
275 +
276 +#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a ML01G100BHI00 NAND flash */
277 +#define CONFIG_SYS_NAND_USE_FLASH_BBT
278 +
279 +#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
280 +#define CONFIG_SYS_NAND_PAGE_COUNT 64
281 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
282 +#define CONFIG_SYS_NAND_OOBSIZE 64
283 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
284 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
285 +
286 +#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
287 +#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
288 +#define CONFIG_LTQ_SPL_MC_TUNE
289 +
290 +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
291 +
292 +/* MTD devices */
293 +#define CONFIG_MTD_PARTITIONS
294 +#define CONFIG_MTD_DEVICE
295 +#define CONFIG_CMD_MTDPARTS
296 +#define MTDIDS_DEFAULT "nand0=nand-xway"
297 +#define MTDPARTS_DEFAULT "mtdparts=nand-xway:0x07e80000@0x100000(UBI)"
298 +
299 +/* UBI */
300 +#define CONFIG_RBTREE
301 +#define CONFIG_CMD_UBI
302 +#define CONFIG_CMD_UBIFS
303 +
304 +/* Environment */
305 +#if defined(CONFIG_SYS_BOOT_NANDSPL)
306 +#define CONFIG_SPL_TPL_OFFS 0x800
307 +#define CONFIG_SPL_TPL_SIZE 0x5000
308 +#define CONFIG_SPL_MC_TUNE_OFFS 0x5800
309 +#define CONFIG_SPL_U_BOOT_OFFS 0x6000
310 +#define CONFIG_SPL_U_BOOT_SIZE 0x3a000
311 +
312 +#define CONFIG_ENV_IS_IN_NAND
313 +#define CONFIG_ENV_OVERWRITE
314 +#define CONFIG_ENV_OFFSET (640 * 1024)
315 +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
316 +#else
317 +#define CONFIG_ENV_IS_NOWHERE
318 +#endif
319 +
320 +#define CONFIG_ENV_SIZE (128 * 1024)
321 +
322 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
323 +
324 +/* Console */
325 +#define CONFIG_LTQ_ADVANCED_CONSOLE
326 +#define CONFIG_BAUDRATE 115200
327 +#define CONFIG_CONSOLE_ASC 1
328 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
329 +
330 +/* Pull in default board configs for Lantiq XWAY VRX200 */
331 +#include <asm/lantiq/config.h>
332 +#include <asm/arch/config.h>
333 +
334 +/* Pull in default OpenWrt configs for Lantiq SoC */
335 +#include "openwrt-lantiq-common.h"
336 +
337 +#undef CONFIG_BOOTCOMMAND
338 +#define CONFIG_BOOTCOMMAND \
339 + "mtdparts default; ubi part UBI; ubi read ${loadaddr} kernel; bootm ${loadaddr}"
340 +
341 +#define CONFIG_EXTRA_ENV_SETTINGS \
342 + CONFIG_ENV_LANTIQ_DEFAULTS
343 +
344 +#endif /* __CONFIG_H */
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