package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch

   1 diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
   2 index 819bd3b..6a2d578 100644
   3 --- a/arch/arm/mach-kirkwood/Kconfig
   4 +++ b/arch/arm/mach-kirkwood/Kconfig
   5 @@ -59,6 +59,9 @@ config TARGET_NSA310
   6  config TARGET_NSA310S
   7         bool "Zyxel NSA310S"
   8
   9 +config TARGET_NSA325
  10 +       bool "Zyxel NSA325 board"
  11 +
  12  endchoice
  13
  14  config SYS_SOC
  15 @@ -82,5 +85,6 @@ source "board/Seagate/goflexhome/Kconfig"
  16  source "board/Seagate/nas220/Kconfig"
  17  source "board/zyxel/nsa310/Kconfig"
  18  source "board/zyxel/nsa310s/Kconfig"
  19 +source "board/zyxel/nsa325/Kconfig"
  20
  21  endif
  22 diff --git a/board/zyxel/nsa325/Kconfig b/board/zyxel/nsa325/Kconfig
  23 new file mode 100644
  24 index 0000000..1fe5ead
  25 --- /dev/null
  26 +++ b/board/zyxel/nsa325/Kconfig
  27 @@ -0,0 +1,12 @@
  28 +if TARGET_NSA325
  29 +
  30 +config SYS_BOARD
  31 +       default "nsa325"
  32 +
  33 +config SYS_VENDOR
  34 +       default "zyxel"
  35 +
  36 +config SYS_CONFIG_NAME
  37 +       default "nsa325"
  38 +
  39 +endif
  40 diff --git a/board/zyxel/nsa325/MAINTAINERS b/board/zyxel/nsa325/MAINTAINERS
  41 new file mode 100644
  42 index 0000000..130b4d9
  43 --- /dev/null
  44 +++ b/board/zyxel/nsa325/MAINTAINERS
  45 @@ -0,0 +1,6 @@
  46 +NSA325 BOARD
  47 +M:     Alberto Bursi <alberto.bursi@outlook.it>
  48 +S:     Maintained
  49 +F:     board/zyxel/nsa325/
  50 +F:     include/configs/nsa325.h
  51 +F:     configs/nsa325_defconfig
  52 diff --git a/board/zyxel/nsa325/Makefile b/board/zyxel/nsa325/Makefile
  53 new file mode 100644
  54 index 0000000..4ee953b
  55 --- /dev/null
  56 +++ b/board/zyxel/nsa325/Makefile
  57 @@ -0,0 +1,13 @@
  58 +#
  59 +# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
  60 +#
  61 +# Based on
  62 +# (C) Copyright 2009
  63 +# Marvell Semiconductor <www.marvell.com>
  64 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  65 +#
  66 +# SPDX-License-Identifier:     GPL-2.0+
  67 +#
  68 +
  69 +obj-y  := nsa325.o
  70 +
  71 diff --git a/board/zyxel/nsa325/kwbimage.cfg b/board/zyxel/nsa325/kwbimage.cfg
  72 new file mode 100644
  73 index 0000000..5a27d38
  74 --- /dev/null
  75 +++ b/board/zyxel/nsa325/kwbimage.cfg
  76 @@ -0,0 +1,78 @@
  77 +# Copyright (C) 2015 bodhi <mibodhi@gmail.com>
  78 +#
  79 +# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2
  80 +#
  81 +# See file CREDITS for list of people who contributed to this
  82 +# project.
  83 +#
  84 +# This program is free software; you can redistribute it and/or
  85 +# modify it under the terms of the GNU General Public License as
  86 +# published by the Free Software Foundation; either version 2 of
  87 +# the License, or (at your option) any later version.
  88 +#
  89 +# This program is distributed in the hope that it will be useful,
  90 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  91 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  92 +# GNU General Public License for more details.
  93 +#
  94 +# You should have received a copy of the GNU General Public License
  95 +# along with this program; if not, write to the Free Software
  96 +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  97 +# MA 02110-1301 USA
  98 +#
  99 +# Refer docs/README.kwimage for more details about how-to configure
 100 +# and create kirkwood boot image
 101 +#
 102 +
 103 +# Boot Media configurations
 104 +#BOOT_FROM     uart
 105 +BOOT_FROM       nand
 106 +NAND_ECC_MODE   default
 107 +NAND_PAGE_SIZE  0x0800
 108 +
 109 +# SOC registers configuration using bootrom header extension
 110 +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
 111 +
 112 +# Configure RGMII-0 interface pad voltage to 1.8V
 113 +DATA 0xFFD100e0 0x1b1b1b9b
 114 +
 115 +#Dram initalization
 116 +DATA 0xFFD01400 0x4301503E      # DDR Configuration register
 117 +DATA 0xFFD01404 0xB9843000      # DDR Controller Control Low
 118 +DATA 0xFFD01408 0x33137777      # DDR Timing (Low)
 119 +DATA 0xFFD0140C 0x16000C55      # DDR Timing (High)
 120 +DATA 0xFFD01410 0x04000000      # DDR Address Control
 121 +DATA 0xFFD01414 0x00000000     #  DDR Open Pages Control
 122 +DATA 0xFFD01418 0x00000000     #  DDR Operation
 123 +DATA 0xFFD0141C 0x00000672     #  DDR Mode
 124 +DATA 0xFFD01420 0x00000004     #  DDR Extended Mode
 125 +DATA 0xFFD01424 0x0000F14F     #  DDR Controller Control High
 126 +DATA 0xFFD01428 0x000D6720     # DDR3 ODT Read Timing
 127 +DATA 0xFFD0147C 0x0000B571     # DDR2 ODT Write Timing
 128 +DATA 0xFFD01504 0x1FFFFFF1      # CS[0]n Size
 129 +DATA 0xFFD01508 0x20000000      # CS[1]n Base address to 512Mb
 130 +DATA 0xFFD0150C 0x1FFFFFF4      # CS[1]n Size 512Mb Window enabled for CS1
 131 +DATA 0xFFD01514 0x00000000      # CS[2]n Size, window disabled
 132 +DATA 0xFFD0151C 0x00000000      # CS[3]n Size, window disabled
 133 +DATA 0xFFD01494 0x00120000      #  DDR ODT Control (Low)
 134 +DATA 0xFFD01498 0x00000000      #  DDR ODT Control (High)
 135 +DATA 0xFFD0149C 0x0000E803      # CPU ODT Control
 136 +
 137 +DATA 0xFFD015D0 0x00000630
 138 +DATA 0xFFD015D4 0x00000046
 139 +DATA 0xFFD015D8 0x00000008
 140 +DATA 0xFFD015DC 0x00000000
 141 +DATA 0xFFD015E0 0x00000023
 142 +DATA 0xFFD015E4 0x00203C18
 143 +DATA 0xFFD01620 0x00384800
 144 +DATA 0xFFD01480 0x00000001
 145 +DATA 0xFFD20134 0x66666666
 146 +DATA 0xFFD20138 0x00066666
 147 +
 148 +#Disable nsa325 hardware watchdog to allow successful kwbooting
 149 +DATA 0xFFD10100 0x00004000 # set GPIO 14 to high to disable the watchdog
 150 +DATA 0xFFD10104 0xFFFFBFFF # set GPIO 14 to output (to block any other input to it)
 151 +
 152 +# End of Header extension
 153 +DATA 0x0 0x0
 154 +
 155 diff --git a/board/zyxel/nsa325/nsa325.c b/board/zyxel/nsa325/nsa325.c
 156 new file mode 100644
 157 index 0000000..4cd1c0f
 158 --- /dev/null
 159 +++ b/board/zyxel/nsa325/nsa325.c
 160 @@ -0,0 +1,265 @@
 161 +/*
 162 + * Copyright (C) 2015 bodhi <mibodhi@gmail.com>
 163 + *
 164 + * Based on
 165 + * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>
 166 + *
 167 + * Based on nsa320.c originall written by
 168 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 169 + *
 170 + * Based on guruplug.c originally written by
 171 + * Siddarth Gore <gores@marvell.com>
 172 + * (C) Copyright 2009
 173 + * Marvell Semiconductor <www.marvell.com>
 174 + *
 175 + * See file CREDITS for list of people who contributed to this
 176 + * project.
 177 + *
 178 + * This program is free software; you can redistribute it and/or
 179 + * modify it under the terms of the GNU General Public License as
 180 + * published by the Free Software Foundation; either version 2 of
 181 + * the License, or (at your option) any later version.
 182 + *
 183 + * This program is distributed in the hope that it will be useful,
 184 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 185 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 186 + * GNU General Public License for more details.
 187 + *
 188 + * You should have received a copy of the GNU General Public License
 189 + * along with this program; if not, write to the Free Software
 190 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 191 + * MA 02110-1301 USA
 192 + */
 193 +
 194 +#include <common.h>
 195 +#include <miiphy.h>
 196 +#include <asm/arch/soc.h>
 197 +#include <asm/arch/mpp.h>
 198 +#include <asm/arch/cpu.h>
 199 +#include <asm/gpio.h>
 200 +#include <asm/io.h>
 201 +#include "nsa325.h"
 202 +#include <asm/arch/gpio.h>
 203 +
 204 +DECLARE_GLOBAL_DATA_PTR;
 205 +
 206 +int board_early_init_f(void)
 207 +{
 208 +       /*
 209 +        * default gpio configuration
 210 +        * There are maximum 64 gpios controlled through 2 sets of registers
 211 +        * the below configuration configures mainly initial LED status
 212 +        */
 213 +       mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,
 214 +                      NSA325_OE_LOW, NSA325_OE_HIGH);
 215 +
 216 +       /* Multi-Purpose Pins Functionality configuration */
 217 +       /* (all LEDs & power off active high) */
 218 +       u32 kwmpp_config[] = {
 219 +               MPP0_NF_IO2,
 220 +               MPP1_NF_IO3,
 221 +               MPP2_NF_IO4,
 222 +               MPP3_NF_IO5,
 223 +               MPP4_NF_IO6,
 224 +               MPP5_NF_IO7,
 225 +               MPP6_SYSRST_OUTn,
 226 +               MPP7_GPO,
 227 +               MPP8_TW_SDA,            /* PCF8563 RTC chip   */
 228 +               MPP9_TW_SCK,            /* connected to TWSI  */
 229 +               MPP10_UART0_TXD,
 230 +               MPP11_UART0_RXD,
 231 +               MPP12_GPO,              /* HDD2 LED (green)   */
 232 +               MPP13_GPIO,             /* HDD2 LED (red)     */
 233 +               MPP14_GPIO,             /* MCU DATA pin (in)  */
 234 +               MPP15_GPIO,             /* USB LED (green)    */
 235 +               MPP16_GPIO,             /* MCU CLK pin (out)  */
 236 +               MPP17_GPIO,             /* MCU ACT pin (out)  */
 237 +               MPP18_NF_IO0,
 238 +               MPP19_NF_IO1,
 239 +               MPP20_GPIO,
 240 +               MPP21_GPIO,             /* USB power          */
 241 +               MPP22_GPIO,
 242 +               MPP23_GPIO,
 243 +               MPP24_GPIO,
 244 +               MPP25_GPIO,
 245 +               MPP26_GPIO,
 246 +               MPP27_GPIO,
 247 +               MPP28_GPIO,             /* SYS LED (green)    */
 248 +               MPP29_GPIO,             /* SYS LED (orange)   */
 249 +               MPP30_GPIO,
 250 +               MPP31_GPIO,
 251 +               MPP32_GPIO,
 252 +               MPP33_GPIO,
 253 +               MPP34_GPIO,
 254 +               MPP35_GPIO,
 255 +               MPP36_GPIO,             /* reset button       */
 256 +               MPP37_GPIO,             /* copy button        */
 257 +               MPP38_GPIO,             /* VID B0             */
 258 +               MPP39_GPIO,             /* COPY LED (green)   */
 259 +               MPP40_GPIO,             /* COPY LED (red)     */
 260 +               MPP41_GPIO,             /* HDD1 LED (green)   */
 261 +               MPP42_GPIO,             /* HDD1 LED (red)     */
 262 +               MPP43_GPIO,             /* HTP pin            */
 263 +               MPP44_GPIO,             /* buzzer             */
 264 +               MPP45_GPIO,             /* VID B1             */
 265 +               MPP46_GPIO,             /* power button       */
 266 +               MPP47_GPIO,             /* HDD2 power         */
 267 +               MPP48_GPIO,             /* power off          */
 268 +               0
 269 +       };
 270 +       kirkwood_mpp_conf(kwmpp_config, NULL);
 271 +       return 0;
 272 +}
 273 +
 274 +int board_init(void)
 275 +{
 276 +
 277 +       /* address of boot parameters */
 278 +       gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 279 +
 280 +       /* This disables the hardware watchdog in the mcu on this board. */
 281 +       kw_gpio_set_valid(14, 1);
 282 +       kw_gpio_direction_output(14, 0);
 283 +       kw_gpio_set_value(14, 1);
 284 +
 285 +       return 0;
 286 +}
 287 +
 288 +#ifdef CONFIG_RESET_PHY_R
 289 +/* Configure and enable MV88E1318 PHY */
 290 +void reset_phy(void)
 291 +{
 292 +       u16 reg;
 293 +       u16 devadr;
 294 +       char *name = "egiga0";
 295 +
 296 +       if (miiphy_set_current_dev(name))
 297 +               return;
 298 +
 299 +       /* command to read PHY dev address */
 300 +       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 301 +               printf("Err..%s could not read PHY dev address\n",
 302 +                       __FUNCTION__);
 303 +               return;
 304 +       }
 305 +
 306 +       /* Set RGMII delay */
 307 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
 308 +       miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);
 309 +       reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
 310 +       miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
 311 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
 312 +
 313 +       /* reset the phy */
 314 +       miiphy_reset(name, devadr);
 315 +
 316 +       /* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */
 317 +       /* and has an MCU attached to the LED[2] via tristate interrupt */
 318 +       reg = 0;
 319 +
 320 +       /* switch to LED register page */
 321 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
 322 +       /* read out LED polarity register */
 323 +       miiphy_read(name, devadr, MV88E1318_LED_POL_REG, &reg);
 324 +       /* clear 4, set 5 - LED2 low, tri-state */
 325 +       reg &= ~(MV88E1318_LED2_4);
 326 +       reg |= (MV88E1318_LED2_5);
 327 +       /* write back LED polarity register */
 328 +       miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg);
 329 +       /* jump back to page 0, per the PHY chip documenation. */
 330 +       miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
 331 +
 332 +       /* Set the phy back to auto-negotiation mode. Onboard mcu sets it as 10Mbits/s on poweroff for WoL function */
 333 +       miiphy_write(name, devadr, 0x4, 0x1e1);
 334 +       miiphy_write(name, devadr, 0x9, 0x300);
 335 +       /* Downshift */
 336 +       miiphy_write(name, devadr, 0x10, 0x3860);
 337 +       miiphy_write(name, devadr, 0x0, 0x9140);
 338 +
 339 +       printf("MV88E1318 PHY initialized on %s\n", name);
 340 +
 341 +}
 342 +#endif /* CONFIG_RESET_PHY_R */
 343 +
 344 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
 345 +void show_boot_progress(int val)
 346 +{
 347 +       struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
 348 +       u32 dout0 = readl(&gpio0->dout);
 349 +       u32 blen0 = readl(&gpio0->blink_en);
 350 +
 351 +       struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
 352 +       u32 dout1 = readl(&gpio1->dout);
 353 +       u32 blen1 = readl(&gpio1->blink_en);
 354 +
 355 +       switch (val) {
 356 +       case BOOTSTAGE_ID_DECOMP_IMAGE:
 357 +               writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);
 358 +               writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);
 359 +               break;
 360 +       case BOOTSTAGE_ID_RUN_OS:
 361 +               writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);
 362 +               writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
 363 +               break;
 364 +       case BOOTSTAGE_ID_NET_START:
 365 +               writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
 366 +               writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
 367 +               break;
 368 +       case BOOTSTAGE_ID_NET_LOADED:
 369 +               writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
 370 +               writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
 371 +               break;
 372 +       case -BOOTSTAGE_ID_NET_NETLOOP_OK:
 373 +       case -BOOTSTAGE_ID_NET_LOADED:
 374 +               writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
 375 +               writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
 376 +               break;
 377 +       default:
 378 +               if (val < 0) {
 379 +                       /* error */
 380 +                       printf("Error occured, error code = %d\n", -val);
 381 +                       writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
 382 +                       writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);
 383 +               }
 384 +               break;
 385 +       }
 386 +}
 387 +#endif
 388 +
 389 +#if defined(CONFIG_KIRKWOOD_GPIO)
 390 +/* Return GPIO button status */
 391 +/*
 392 +un-pressed:
 393 + gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear )
 394 + gpio-37 (Copy Button  ) in hi (act lo) - IRQ edge (clear )
 395 + gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear )
 396 +pressed
 397 + gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear )
 398 + gpio-37 (Copy Button  ) in lo (act hi) - IRQ edge (clear )
 399 + gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear )
 400 +*/
 401 +
 402 +static int
 403 +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 404 +{
 405 +       if (strcmp(argv[1], "power") == 0) {
 406 +                       kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK);
 407 +                       kw_gpio_direction_input(BTN_POWER);
 408 +                       return !kw_gpio_get_value(BTN_POWER);
 409 +       }
 410 +       else if (strcmp(argv[1], "reset") == 0)
 411 +               return kw_gpio_get_value(BTN_RESET);
 412 +       else if (strcmp(argv[1], "copy") == 0)
 413 +               return kw_gpio_get_value(BTN_COPY);
 414 +       else
 415 +               return -1;
 416 +}
 417 +
 418 +
 419 +U_BOOT_CMD(button, 2, 0, do_read_button,
 420 +          "Return GPIO button status 0=off 1=on",
 421 +          "- button power|reset|copy: test buttons states\n"
 422 +);
 423 +
 424 +#endif
 425 +
 426 diff --git a/board/zyxel/nsa325/nsa325.h b/board/zyxel/nsa325/nsa325.h
 427 new file mode 100644
 428 index 0000000..996653e
 429 --- /dev/null
 430 +++ b/board/zyxel/nsa325/nsa325.h
 431 @@ -0,0 +1,77 @@
 432 +/*
 433 + * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>
 434 + *
 435 + * Based on nsa320.h originall written by
 436 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 437 + *
 438 + * Based on guruplug.h originally written by
 439 + * Siddarth Gore <gores@marvell.com>
 440 + * (C) Copyright 2009
 441 + * Marvell Semiconductor <www.marvell.com>
 442 + *
 443 + * See file CREDITS for list of people who contributed to this
 444 + * project.
 445 + *
 446 + * This program is free software; you can redistribute it and/or
 447 + * modify it under the terms of the GNU General Public License as
 448 + * published by the Free Software Foundation; either version 2 of
 449 + * the License, or (at your option) any later version.
 450 + *
 451 + * This program is distributed in the hope that it will be useful,
 452 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 453 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 454 + * GNU General Public License for more details.
 455 + *
 456 + * You should have received a copy of the GNU General Public License
 457 + * along with this program; if not, write to the Free Software
 458 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 459 + * MA 02110-1301 USA
 460 + */
 461 +
 462 +#ifndef __NSA325_H
 463 +#define __NSA325_H
 464 +
 465 +/* low GPIO's */
 466 +#define HDD2_GREEN_LED         (1 << 12)
 467 +#define HDD2_RED_LED           (1 << 13)
 468 +#define USB_GREEN_LED          (1 << 15)
 469 +#define USB_POWER              (1 << 21)
 470 +#define SYS_GREEN_LED          (1 << 28)
 471 +#define SYS_ORANGE_LED         (1 << 29)
 472 +
 473 +#define PIN_USB_GREEN_LED      15
 474 +#define PIN_USB_POWER          21
 475 +
 476 +#define NSA325_OE_LOW          (~(HDD2_GREEN_LED | HDD2_RED_LED | \
 477 +                                  USB_GREEN_LED | USB_POWER | \
 478 +                                  SYS_GREEN_LED | SYS_ORANGE_LED))
 479 +#define NSA325_VAL_LOW         (SYS_GREEN_LED | USB_POWER)
 480 +
 481 +/* high GPIO's */
 482 +#define COPY_GREEN_LED         (1 << 7)
 483 +#define COPY_RED_LED           (1 << 8)
 484 +#define HDD1_GREEN_LED         (1 << 9)
 485 +#define HDD1_RED_LED           (1 << 10)
 486 +#define HDD2_POWER          (1 << 15)
 487 +#define WATCHDOG_SIGNAL     (1 << 14)
 488 +
 489 +#define NSA325_OE_HIGH         (~(COPY_GREEN_LED | COPY_RED_LED | \
 490 +                                  HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL ))
 491 +#define NSA325_VAL_HIGH                (WATCHDOG_SIGNAL | HDD2_POWER)
 492 +
 493 +/* PHY related */
 494 +#define MV88E1318_PGADR_REG            22
 495 +#define MV88E1318_MAC_CTRL_PG  2
 496 +#define MV88E1318_MAC_CTRL_REG 21
 497 +#define MV88E1318_RGMII_TXTM_CTRL      (1 << 4)
 498 +#define MV88E1318_RGMII_RXTM_CTRL      (1 << 5)
 499 +#define MV88E1318_LED_PG        3
 500 +#define MV88E1318_LED_POL_REG  17
 501 +#define MV88E1318_LED2_4           (1 << 4)
 502 +#define MV88E1318_LED2_5           (1 << 5)
 503 +
 504 +#define BTN_POWER                              46
 505 +#define BTN_RESET                              36
 506 +#define BTN_COPY                               37
 507 +
 508 +#endif /* __NSA325_H */
 509 diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig
 510 new file mode 100644
 511 index 0000000..48e09cc
 512 --- /dev/null
 513 +++ b/configs/nsa325_defconfig
 514 @@ -0,0 +1,18 @@
 515 +CONFIG_ARM=y
 516 +CONFIG_KIRKWOOD=y
 517 +CONFIG_TARGET_NSA325=y
 518 +CONFIG_BOOTDELAY=3
 519 +CONFIG_SYS_PROMPT="NSA325> "
 520 +# CONFIG_CMD_IMLS is not set
 521 +# CONFIG_CMD_FLASH is not set
 522 +CONFIG_SYS_NS16550=y
 523 +CONFIG_CMD_FDT=y
 524 +CONFIG_OF_LIBFDT=y
 525 +CONFIG_CMD_SETEXPR=y
 526 +CONFIG_CMD_DHCP=y
 527 +CONFIG_CMD_NAND=y
 528 +CONFIG_CMD_PING=y
 529 +CONFIG_CMD_USB=y
 530 +CONFIG_USB=y
 531 +CONFIG_CMD_FAT=y
 532 +CONFIG_USB_STORAGE=y
 533 \ No newline at end of file
 534 diff --git a/include/configs/nsa325.h b/include/configs/nsa325.h
 535 new file mode 100644
 536 index 0000000..e5a8e2a
 537 --- /dev/null
 538 +++ b/include/configs/nsa325.h
 539 @@ -0,0 +1,170 @@
 540 +/*
 541 + * (C) Copyright 2016 bodhi <mibodhi@gmail.com>
 542 + *
 543 + * Based on
 544 + * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
 545 + * Based on
 546 + * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
 547 + *
 548 + * Based on guruplug.h originally written by
 549 + * Siddarth Gore <gores@marvell.com>
 550 + * (C) Copyright 2009
 551 + * Marvell Semiconductor <www.marvell.com>
 552 + *
 553 + * See file CREDITS for list of people who contributed to this
 554 + * project.
 555 + *
 556 + * This program is free software; you can redistribute it and/or
 557 + * modify it under the terms of the GNU General Public License as
 558 + * published by the Free Software Foundation; either version 2 of
 559 + * the License, or (at your option) any later version.
 560 + *
 561 + * This program is distributed in the hope that it will be useful,
 562 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 563 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 564 + * GNU General Public License for more details.
 565 + *
 566 + * You should have received a copy of the GNU General Public License
 567 + * along with this program; if not, write to the Free Software
 568 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 569 + * MA 02110-1301 USA
 570 + */
 571 +
 572 +#ifndef _CONFIG_NSA325_H
 573 +#define _CONFIG_NSA325_H
 574 +
 575 +/*
 576 + * Version number information
 577 + */
 578 +#define CONFIG_IDENT_STRING    "\nZyXEL NSA325 2-Bay Power Media Server"
 579 +
 580 +/*
 581 + * High Level Configuration Options (easy to change)
 582 + */
 583 +#define CONFIG_FEROCEON_88FR131        1       /* CPU Core subversion */
 584 +#define CONFIG_KIRKWOOD                1       /* SOC Family Name */
 585 +#define CONFIG_KW88F6281       1       /* SOC Name */
 586 +
 587 +#define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
 588 +
 589 +/*
 590 + * Misc Configuration Options
 591 + */
 592 +#define CONFIG_SHOW_BOOT_PROGRESS 1    /* boot progess display (LED's) */
 593 +
 594 +/*
 595 + * Commands configuration
 596 + */
 597 +#define CONFIG_SYS_NO_FLASH             /* Declare no flash (NOR/SPI) */
 598 +#define CONFIG_SYS_MVFS                 /* Picks up Filesystem from mv-common.h */
 599 +#define CONFIG_CMD_DHCP
 600 +#define CONFIG_CMD_ENV
 601 +#define CONFIG_CMD_IDE
 602 +#define CONFIG_CMD_MII
 603 +#define CONFIG_CMD_NAND
 604 +#define CONFIG_CMD_PING
 605 +#define CONFIG_CMD_USB
 606 +#define CONFIG_CMD_DATE
 607 +#define CONFIG_SYS_LONGHELP
 608 +#define CONFIG_PREBOOT
 609 +#define CONFIG_SYS_HUSH_PARSER
 610 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 611 +
 612 +/*
 613 + * mv-common.h should be defined after CMD configs since it used them
 614 + * to enable certain macros
 615 + */
 616 +#include "mv-common.h"
 617 +
 618 +#undef CONFIG_SYS_PROMPT       /* previously defined in mv-common.h */
 619 +#define CONFIG_SYS_PROMPT      "NSA325> "      /* Command Prompt */
 620 +
 621 +/*
 622 + *  Environment variables configurations
 623 + */
 624 +#ifdef CONFIG_CMD_NAND
 625 +#define CONFIG_ENV_IS_IN_NAND          1
 626 +#define CONFIG_ENV_SECT_SIZE           0x20000         /* 128K */
 627 +#else
 628 +#define CONFIG_ENV_IS_NOWHERE          1               /* if env in SDRAM */
 629 +#endif
 630 +/*
 631 + * max 4k env size is enough, but in case of nand
 632 + * it has to be rounded to sector size
 633 + */
 634 +#define CONFIG_ENV_SIZE                        0x20000         /* 128k */
 635 +#define CONFIG_ENV_ADDR                        0xc0000
 636 +#define CONFIG_ENV_OFFSET              0xc0000 /* env starts here */
 637 +
 638 +/*
 639 + * Default environment variables
 640 + */
 641 +#define CONFIG_BOOTCOMMAND \
 642 +       "ubi part ubi; " \
 643 +       "ubi read 0x800000 kernel; " \
 644 +       "bootm 0x800000"
 645 +
 646 +#define CONFIG_MTDPARTS \
 647 +       "mtdparts=orion_nand:" \
 648 +       "0x0c0000(uboot)," \
 649 +       "0x80000(uboot_env)," \
 650 +       "0x7ec0000(ubi)\0"
 651 +
 652 +#define CONFIG_EXTRA_ENV_SETTINGS \
 653 +       "console=console=ttyS0,115200\0"        \
 654 +       "mtdids=nand0=orion_nand\0"             \
 655 +       "mtdparts="CONFIG_MTDPARTS              \
 656 +       "bootargs_root=\0"
 657 +
 658 +/*
 659 + * Ethernet Driver configuration
 660 + */
 661 +#ifdef CONFIG_CMD_NET
 662 +#define CONFIG_MVGBE_PORTS             {1, 0}  /* enable port 0 only */
 663 +#define CONFIG_PHY_BASE_ADR            0x1
 664 +#define CONFIG_PHY_GIGE
 665 +#define CONFIG_NETCONSOLE
 666 +#endif /* CONFIG_CMD_NET */
 667 +
 668 +/*
 669 + * SATA Driver configuration
 670 + */
 671 +#ifdef CONFIG_MVSATA_IDE
 672 +#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
 673 +#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
 674 +#endif /* CONFIG_MVSATA_IDE */
 675 +
 676 +/*
 677 + * File system
 678 + */
 679 +#define CONFIG_CMD_EXT2
 680 +#define CONFIG_CMD_EXT4
 681 +#define CONFIG_CMD_FAT
 682 +#define CONFIG_CMD_JFFS2
 683 +#define CONFIG_JFFS2_NAND
 684 +#define CONFIG_JFFS2_LZO
 685 +#define CONFIG_CMD_UBI
 686 +#define CONFIG_CMD_UBIFS
 687 +#define CONFIG_RBTREE
 688 +#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 689 +#define CONFIG_MTD_PARTITIONS
 690 +#define CONFIG_CMD_MTDPARTS
 691 +#define CONFIG_LZO
 692 +
 693 +/*
 694 + * EFI partition
 695 + */
 696 +#define CONFIG_EFI_PARTITION
 697 +
 698 +/*
 699 + *  Date Time
 700 + */
 701 +#ifdef CONFIG_CMD_DATE
 702 +#define CONFIG_RTC_MV
 703 +#define CONFIG_CMD_SNTP
 704 +#define CONFIG_CMD_DNS
 705 +#endif /* CONFIG_CMD_DATE */
 706 +
 707 +#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
 708 +
 709 +#endif /* _CONFIG_NSA325_H */