rockchip: add Radxa CM3 IO board support
[openwrt/staging/jow.git] / target / linux / ramips / dts / rt3662_engenius_esr600h.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "rt3883.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8
9 / {
10 compatible = "engenius,esr600h", "ralink,rt3662-soc", "ralink,rt3883-soc";
11 model = "EnGenius ESR600H";
12
13 aliases {
14 led-boot = &led_power;
15 led-failsafe = &led_power;
16 led-running = &led_power;
17 led-upgrade = &led_power;
18 };
19
20 leds {
21 compatible = "gpio-leds";
22
23 led_power: power {
24 function = LED_FUNCTION_POWER;
25 color = <LED_COLOR_ID_BLUE>;
26 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
27 default-state = "on";
28 };
29
30 wps {
31 function = LED_FUNCTION_WPS;
32 color = <LED_COLOR_ID_BLUE>;
33 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
34 };
35 };
36
37 keys {
38 compatible = "gpio-keys-polled";
39 poll-interval = <100>;
40
41 reset-wps {
42 label = "reset-wps";
43 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
44 linux,code = <KEY_RESTART>;
45 };
46 };
47
48 gpio_export {
49 compatible = "gpio-export";
50 #size-cells = <0>;
51
52 usb {
53 gpio-export,name = "usb";
54 gpio-export,output = <1>;
55 gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
56 };
57 };
58 };
59
60 &gpio1 {
61 status = "okay";
62 };
63
64 &spi0 {
65 status = "okay";
66
67 flash@0 {
68 compatible = "jedec,spi-nor";
69 reg = <0>;
70 spi-max-frequency = <20000000>;
71
72 partitions {
73 compatible = "fixed-partitions";
74 #address-cells = <1>;
75 #size-cells = <1>;
76
77 partition@0 {
78 label = "u-boot";
79 reg = <0x0 0x30000>;
80 read-only;
81 };
82
83 partition@30000 {
84 label = "u-boot-env";
85 reg = <0x30000 0x1000>;
86 };
87
88 partition@32000 {
89 label = "config";
90 reg = <0x32000 0xe000>;
91 read-only;
92 };
93
94 factory: partition@40000 {
95 label = "factory";
96 reg = <0x40000 0x10000>;
97 read-only;
98
99 nvmem-layout {
100 compatible = "fixed-layout";
101 #address-cells = <1>;
102 #size-cells = <1>;
103
104 eeprom_factory_0: eeprom@0 {
105 reg = <0x0 0x200>;
106 };
107
108 eeprom_factory_8000: eeprom@8000 {
109 reg = <0x8000 0x200>;
110 };
111 };
112 };
113
114 partition@50000 {
115 compatible = "denx,uimage";
116 label = "firmware";
117 reg = <0x50000 0x7b0000>;
118 };
119 };
120 };
121 };
122
123 &state_default {
124 gpio {
125 groups = "i2c", "jtag", "uartf";
126 function = "gpio";
127 };
128 };
129
130 &ethernet {
131 status = "okay";
132
133 port@0 {
134 phy-handle = <&phy0>;
135 phy-mode = "rgmii";
136 };
137
138 mdio-bus {
139 status = "okay";
140
141 phy0: ethernet-phy@0 {
142 reg = <0>;
143 phy-mode = "rgmii";
144
145 qca,ar8327-initvals = <
146 0x04 0x07600000 /* PORT0 PAD MODE CTRL */
147 0x0c 0x07600000 /* PORT6 PAD MODE CTRL */
148 0x10 0x40000000 /* Power-on Strapping: 176-pin interface configuration */
149 0x50 0xc437c437 /* LED Control Register 0 */
150 0x54 0xc337c337 /* LED Control Register 1 */
151 0x58 0x00000000 /* LED Control Register 2 */
152 0x5c 0x03ffff00 /* LED Control Register 3 */
153 0x7c 0x0000007e /* PORT0_STATUS */
154 0x94 0x0000007e /* PORT6 STATUS */
155 >;
156 };
157 };
158 };
159
160 &pci {
161 status = "okay";
162 };
163
164 &pci1 {
165 status = "okay";
166
167 wifi@0,0 {
168 compatible = "pci1814,3091";
169 reg = <0x10000 0 0 0 0>;
170 ralink,5ghz = <0>;
171 nvmem-cells = <&eeprom_factory_8000>;
172 nvmem-cell-names = "eeprom";
173 };
174 };
175
176 &wmac {
177 ralink,2ghz = <0>;
178 nvmem-cells = <&eeprom_factory_0>;
179 nvmem-cell-names = "eeprom";
180 };
181
182 &ehci {
183 status = "okay";
184 };
185
186 &ohci {
187 status = "okay";
188 };